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Mon, 11 Mar 2024 06:28:06 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=s31663417; t=1710098882; x=1710703682; i=j.neuschaefer@gmx.net; bh=Lc1pMRgsV+StSf5fgFNpvmYafFqXYMKdh+E4JPDHkIM=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To: References; b=KSMmSzhZdH/DubdvIiLid0lUEXJbPY1f7gSdBwVylQeesC7Ki7Vkg2hTobC81NiZ dAnoyMhChLWm4d5V5ffU4ey/o6abf6qGNmj8UdPqPdU0NJrwTeOaan97wI6InDfSM adEJDl1YDm/FtbzeiP1sWo6jNLu1nQCQLyyA5lpL0cCjtK98RnS7dl0BVSHje4yaU WwMM4IQBuPCPh9PCYg8/oGKEuqFE/zMIqv8S5dx2ykU+IDy/mnzL+8VcXp3merB4V T+cmVP8dVFaWpMSjhCmLYva+Ff/FO8kZIGPrirNMS2fDIu+rhsr8I+5s+ji5v//rI Bfj4FbJKIdNf3ls1rA== X-UI-Sender-Class: 724b4f7f-cbec-4199-ad4e-598c01a50d3a Received: from probook ([78.35.216.168]) by mail.gmx.net (mrgmx004 [212.227.17.190]) with ESMTPSA (Nemesis) id 1MgNh7-1rBBBJ0KLv-00hvec; Sun, 10 Mar 2024 20:22:06 +0100 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-clk@vger.kernel.org, openbmc@lists.ozlabs.org Subject: [PATCH v10 4/4] ARM: dts: wpcm450: Switch clocks to clock controller Date: Sun, 10 Mar 2024 20:21:02 +0100 Message-ID: <20240310192108.2747084-5-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240310192108.2747084-1-j.neuschaefer@gmx.net> References: <20240310192108.2747084-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:CZOP/2JyhuYMjvSoJftgiK/2nFIgRon1+neVh/LZn4z7J6VfK+Y phi/XYNwa4bSKC6jy9/3KudhpuaCSWhKSnAvYt0goG/vWKXb0E9SIIDCkWj6VF420nX5Wa6 Np3/bXESt4ZTzvjlR4m8nFawznti+83B1GljuO5cYG8N+gcWJbGj0tbZN83upD3iWlEP/GK ZseouWgpoYKKzhSS+0NvQ== X-Spam-Flag: NO UI-OutboundReport: notjunk:1;M01:P0:tGAWbs6apBk=;uxYWua3QHt2dYmjgOorlzJcIWhI 44mZrq34upeYHz1w2eJ3eXA8+jts2ywcQ7KX3xbNaZMDg2OkxM9IKAkP9Lf0+h6W3Oduxzccb W5oiMZK8TFnxvVEgSnFnwoEgYnaO1Mj0myZbo9ukY0OIB1JFHEppcvzt2vp9TjNZpuG7PbZRo V/lB4UYPvaERXwGfKbd7N+f6lC4lQc0RflmXAljmmc/3vYdjtu0XmJU7awU8JFAlLtiqpYf5d g8z+7WdGrakDGZ3mtYs0iwN+4/QMjNoHwh/F5ckEd3GGcOHeJeupbWH4U9ef6m8XqSY3qujMS ww3EVkQsQz36+KojkK+KCVvPQt7WCEPsuR0iZNesQQ+1S1WMUe+B+8eiRLIaMvouXPbmHNnvV EJlSUqbZBAuPe9s552zsYp+LNrviy3tgID71fK3Qvoo11PZkGApC/Iwnj9Dvg0jqNRl+xddF+ okKm7QAt6Vxbr3pZxsxMZcWxIZR1SOGLK42v0dVHFxpubg0OoX5k2FPM8aBr83afRwiXIP9jE quHUWlPo8FXA9wU6us+EzdsquVDtVA0lcF4QdF9NhPfvsd6VfN7rLA7/qr8OYtHX270Ugr2AK MxFFSXk6Toh5XdQ+iGdzOn4y6qw/G1WidjVvHYRmt66QzMq8A6DzRchIutnH95BfDPHCC+nas /+X+koYNlGV9vWmPju2hhyhnuexO/9mPNccThYAhUki0r/dXt5xnI5S8R1S31FGGNmLqWBZcH GwRHBP8u8SnFRBuWnvcTqxe0e28Zx/se2KRaWGS51BYwXv2/j9hWUWU+ukOMgYpjAOYxp88K3 TlNoAqCjTKQD9zXK7+namTotDPifxXNB34dC3HhXVw+zQ= X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Conor Dooley , Wim Van Sebroeck , linux-watchdog@vger.kernel.org, Stephen Boyd , Patrick Venture , Michael Turquette , Daniel Lezcano , linux-kernel@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Avi Fishman , Rob Herring , Christophe JAILLET , Benjamin Fair , Krzysztof Kozlowski , Philipp Zabel , Thomas Gleixner , Tali Perry , Guenter Roeck , Tomer Maimon Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" This change is incompatible with older kernels because it requires the clock controller driver, but I think that's acceptable because WPCM450 support is generally still in an early phase. Signed-off-by: Jonathan Neuschäfer --- It's probably best to delay merging of this patch until after the driver is merged; I'm including it here for review, and in case someone want's to set up a shared branch between the clock and devicetree parts. v10: - Reintroducing this patch as part of the clock/reset controller series --- .../arm/boot/dts/nuvoton/nuvoton-wpcm450.dtsi | 22 +++++++++---------- 1 file changed, 10 insertions(+), 12 deletions(-) -- 2.43.0 diff --git a/arch/arm/boot/dts/nuvoton/nuvoton-wpcm450.dtsi b/arch/arm/boot/dts/nuvoton/nuvoton-wpcm450.dtsi index 9dfdd8f67319d3..7e3ea8b31151b3 100644 --- a/arch/arm/boot/dts/nuvoton/nuvoton-wpcm450.dtsi +++ b/arch/arm/boot/dts/nuvoton/nuvoton-wpcm450.dtsi @@ -2,6 +2,7 @@ // Copyright 2021 Jonathan Neuschäfer #include +#include / { compatible = "nuvoton,wpcm450"; @@ -30,13 +31,6 @@ cpu@0 { }; }; - clk24m: clock-24mhz { - /* 24 MHz dummy clock */ - compatible = "fixed-clock"; - clock-frequency = <24000000>; - #clock-cells = <0>; - }; - refclk: clock-48mhz { /* 48 MHz reference oscillator */ compatible = "fixed-clock"; @@ -70,7 +64,7 @@ serial0: serial@b8000000 { reg = <0xb8000000 0x20>; reg-shift = <2>; interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk24m>; + clocks = <&clk WPCM450_CLK_UART0>; pinctrl-names = "default"; pinctrl-0 = <&bsp_pins>; status = "disabled"; @@ -81,7 +75,7 @@ serial1: serial@b8000100 { reg = <0xb8000100 0x20>; reg-shift = <2>; interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk24m>; + clocks = <&clk WPCM450_CLK_UART1>; status = "disabled"; }; @@ -89,14 +83,18 @@ timer0: timer@b8001000 { compatible = "nuvoton,wpcm450-timer"; interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; reg = <0xb8001000 0x1c>; - clocks = <&clk24m>; + clocks = <&clk WPCM450_CLK_TIMER0>, + <&clk WPCM450_CLK_TIMER1>, + <&clk WPCM450_CLK_TIMER2>, + <&clk WPCM450_CLK_TIMER3>, + <&clk WPCM450_CLK_TIMER4>; }; watchdog0: watchdog@b800101c { compatible = "nuvoton,wpcm450-wdt"; interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; reg = <0xb800101c 0x4>; - clocks = <&clk24m>; + clocks = <&clk WPCM450_CLK_WDT>; }; aic: interrupt-controller@b8002000 { @@ -480,7 +478,7 @@ fiu: spi-controller@c8000000 { #size-cells = <0>; reg = <0xc8000000 0x1000>, <0xc0000000 0x4000000>; reg-names = "control", "memory"; - clocks = <&clk 0>; + clocks = <&clk WPCM450_CLK_FIU>; nuvoton,shm = <&shm>; status = "disabled"; };