@@ -58,6 +58,8 @@ clk: clock-controller@f0801000 {
compatible = "nuvoton,npcm845-clk";
#clock-cells = <1>;
reg = <0x0 0xf0801000 0x0 0x1000>;
+ clocks = <&refclk>;
+ clock-names = "refclk";
};
apb {
@@ -81,7 +83,7 @@ timer0: timer@8000 {
compatible = "nuvoton,npcm845-timer";
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x8000 0x1C>;
- clocks = <&clk NPCM8XX_CLK_REFCLK>;
+ clocks = <&refclk>;
clock-names = "refclk";
};
@@ -153,7 +155,7 @@ watchdog0: watchdog@801c {
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x801c 0x4>;
status = "disabled";
- clocks = <&clk NPCM8XX_CLK_REFCLK>;
+ clocks = <&refclk>;
syscon = <&gcr>;
};
@@ -162,7 +164,7 @@ watchdog1: watchdog@901c {
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x901c 0x4>;
status = "disabled";
- clocks = <&clk NPCM8XX_CLK_REFCLK>;
+ clocks = <&refclk>;
syscon = <&gcr>;
};
@@ -171,7 +173,7 @@ watchdog2: watchdog@a01c {
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xa01c 0x4>;
status = "disabled";
- clocks = <&clk NPCM8XX_CLK_REFCLK>;
+ clocks = <&refclk>;
syscon = <&gcr>;
};
};
@@ -19,6 +19,12 @@ chosen {
memory {
reg = <0x0 0x0 0x0 0x40000000>;
};
+
+ refclk: refclk-25mhz {
+ compatible = "fixed-clock";
+ clock-frequency = <25000000>;
+ #clock-cells = <0>;
+ };
};
&serial0 {
Add 25Mhz reference clock since the reference clock in not a part of Nuvoton BMC NPCM8XX SoC. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> --- .../arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi | 10 ++++++---- arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts | 6 ++++++ 2 files changed, 12 insertions(+), 4 deletions(-)