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[1.34.21.66]) by smtp.gmail.com with ESMTPSA id j12-20020a056a00130c00b0068fece22469sm5582116pfu.4.2023.11.20.01.17.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Nov 2023 01:17:52 -0800 (PST) From: Cosmo Chou To: brendan.higgins@linux.dev, benh@kernel.crashing.org, joel@jms.id.au, andi.shyti@kernel.org, andrew@codeconstruct.com.au, linux@roeck-us.net, wsa@kernel.org, jae.hyun.yoo@linux.intel.com Subject: [PATCH] i2c: aspeed: Acknowledge Tx ack late when in SLAVE_READ_PROCESSED Date: Mon, 20 Nov 2023 17:17:46 +0800 Message-Id: <20231120091746.2866232-1-chou.cosmo@gmail.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Mailman-Approved-At: Tue, 21 Nov 2023 18:01:51 +1100 X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-aspeed@lists.ozlabs.org, chou.cosmo@gmail.com, openbmc@lists.ozlabs.org, linux-kernel@vger.kernel.org, cosmo.chou@quantatw.com, linux-i2c@vger.kernel.org, linux-arm-kernel@lists.infradead.org Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" commit 2be6b47211e1 ("i2c: aspeed: Acknowledge most interrupts early in interrupt handler") moved most interrupt acknowledgments to the start of the interrupt handler to avoid race conditions. However, slave Tx ack status shouldn't be cleared before SLAVE_READ_PROCESSED is handled. Acknowledge Tx ack status after handling SLAVE_READ_PROCESSED to fix the problem that the next byte is not sent correctly. Fixes: 2be6b47211e1 ("i2c: aspeed: Acknowledge most interrupts early in interrupt handler") Signed-off-by: Cosmo Chou --- drivers/i2c/busses/i2c-aspeed.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/drivers/i2c/busses/i2c-aspeed.c b/drivers/i2c/busses/i2c-aspeed.c index 28e2a5fc4528..c2d74e4b7e50 100644 --- a/drivers/i2c/busses/i2c-aspeed.c +++ b/drivers/i2c/busses/i2c-aspeed.c @@ -337,6 +337,12 @@ static u32 aspeed_i2c_slave_irq(struct aspeed_i2c_bus *bus, u32 irq_status) break; } + /* Ack Tx ack */ + if (irq_handled & ASPEED_I2CD_INTR_TX_ACK) { + writel(ASPEED_I2CD_INTR_TX_ACK, bus->base + ASPEED_I2C_INTR_STS_REG); + readl(bus->base + ASPEED_I2C_INTR_STS_REG); + } + return irq_handled; } #endif /* CONFIG_I2C_SLAVE */ @@ -602,13 +608,18 @@ static u32 aspeed_i2c_master_irq(struct aspeed_i2c_bus *bus, u32 irq_status) static irqreturn_t aspeed_i2c_bus_irq(int irq, void *dev_id) { struct aspeed_i2c_bus *bus = dev_id; - u32 irq_received, irq_remaining, irq_handled; + u32 irq_received, irq_remaining, irq_handled, irq_acked; spin_lock(&bus->lock); irq_received = readl(bus->base + ASPEED_I2C_INTR_STS_REG); /* Ack all interrupts except for Rx done */ - writel(irq_received & ~ASPEED_I2CD_INTR_RX_DONE, - bus->base + ASPEED_I2C_INTR_STS_REG); + irq_acked = irq_received & ~ASPEED_I2CD_INTR_RX_DONE; +#if IS_ENABLED(CONFIG_I2C_SLAVE) + /* shouldn't ack Slave Tx Ack before it's handled */ + if (bus->slave_state == ASPEED_I2C_SLAVE_READ_PROCESSED) + irq_acked &= ~ASPEED_I2CD_INTR_TX_ACK; +#endif + writel(irq_acked, bus->base + ASPEED_I2C_INTR_STS_REG); readl(bus->base + ASPEED_I2C_INTR_STS_REG); irq_received &= ASPEED_I2CD_INTR_RECV_MASK; irq_remaining = irq_received;