@@ -50,9 +50,9 @@
#define LPC_HICR0_LPC2E BIT(6)
#define LPC_HICR0_LPC1E BIT(5)
#define LPC_HICR2 0x008
-#define LPC_HICR2_IBFIF3 BIT(3)
-#define LPC_HICR2_IBFIF2 BIT(2)
-#define LPC_HICR2_IBFIF1 BIT(1)
+#define LPC_HICR2_IBFIE3 BIT(3)
+#define LPC_HICR2_IBFIE2 BIT(2)
+#define LPC_HICR2_IBFIE1 BIT(1)
#define LPC_HICR4 0x010
#define LPC_HICR4_LADR12AS BIT(7)
#define LPC_HICR4_KCSENBL BIT(2)
@@ -83,7 +83,7 @@
#define LPC_STR2 0x040
#define LPC_STR3 0x044
#define LPC_HICRB 0x100
-#define LPC_HICRB_IBFIF4 BIT(1)
+#define LPC_HICRB_IBFIE4 BIT(1)
#define LPC_HICRB_LPC4E BIT(0)
#define LPC_HICRC 0x104
#define LPC_HICRC_ID4IRQX_MASK GENMASK(7, 4)
@@ -383,20 +383,20 @@ static void aspeed_kcs_irq_mask_update(struct kcs_bmc_device *kcs_bmc, u8 mask,
switch (kcs_bmc->channel) {
case 1:
- regmap_update_bits(priv->map, LPC_HICR2, LPC_HICR2_IBFIF1,
- enable * LPC_HICR2_IBFIF1);
+ regmap_update_bits(priv->map, LPC_HICR2, LPC_HICR2_IBFIE1,
+ enable * LPC_HICR2_IBFIE1);
return;
case 2:
- regmap_update_bits(priv->map, LPC_HICR2, LPC_HICR2_IBFIF2,
- enable * LPC_HICR2_IBFIF2);
+ regmap_update_bits(priv->map, LPC_HICR2, LPC_HICR2_IBFIE2,
+ enable * LPC_HICR2_IBFIE2);
return;
case 3:
- regmap_update_bits(priv->map, LPC_HICR2, LPC_HICR2_IBFIF3,
- enable * LPC_HICR2_IBFIF3);
+ regmap_update_bits(priv->map, LPC_HICR2, LPC_HICR2_IBFIE3,
+ enable * LPC_HICR2_IBFIE3);
return;
case 4:
- regmap_update_bits(priv->map, LPC_HICRB, LPC_HICRB_IBFIF4,
- enable * LPC_HICRB_IBFIF4);
+ regmap_update_bits(priv->map, LPC_HICRB, LPC_HICRB_IBFIE4,
+ enable * LPC_HICRB_IBFIE4);
return;
default:
pr_warn("%s: Unsupported channel: %d", __func__, kcs_bmc->channel);