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bh=yDL40uP+kAC3ujsM0EdFsGaQpPzT9QQURdIX1zfn8SM=; b=cSeb0tVzj5NQRzDhDC10ooQOVi3J68HWx7sHFkVW0+CFQSU1jg5IIdFzu89Jhdgyv3 rlDQnBW3mMVjjBa8LDTRpyuewRyX+gdWQc+SXQviWzRa2Bjn9WoKlmi95hrOj1+1H7mv Q/cXINGXkCETHsjOjDLM4Cxbx+CmDZqPqAs2eBCYawuiyE7B74yWI5Txp5sID62qVkrm M5OLUtxOlCXsLb4KaIy8p82i0dKfC+hllrdPIugE2Wv4CeymVIDlB3OipR6NY0Dgvtkx S7hz0JT1RzNXLnJybujFCK4dQm6+oaybhQsPGmAIway39ELN66d49HKm3edamhxY8Teu kD/g== X-Gm-Message-State: AOJu0Yxx3iaJT+ybEqzPtWTTudP3tJcI7CtqwfKZY7Tc9CD2po5zQoFq ObVkmd/JFSiTOLd4LmBxgG4= X-Google-Smtp-Source: AGHT+IGPI0C1cwkNW52VsX90UmIRRS7/kDnveimVHYzyudFdRLFzW3L08ZWGf9t+sYXuJduWkE/VYw== X-Received: by 2002:a05:6a21:1448:b0:17a:d173:42f1 with SMTP id oc8-20020a056a21144800b0017ad17342f1mr1464806pzb.44.1698138418256; Tue, 24 Oct 2023 02:06:58 -0700 (PDT) Received: from cs20-buildserver.lan ([1.200.144.223]) by smtp.gmail.com with ESMTPSA id c24-20020a170902d91800b001c9ab91d3d7sm7055324plz.37.2023.10.24.02.06.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Oct 2023 02:06:57 -0700 (PDT) From: Jim Liu To: jim.t90615@gmail.com, JJLIU0@nuvoton.com, linus.walleij@linaro.org, krzysztof.kozlowski+dt@linaro.org, brgl@bgdev.pl Subject: [PATCH v6 0/3] Add Nuvoton NPCM SGPIO feature Date: Tue, 24 Oct 2023 17:06:28 +0800 Message-Id: <20231024090631.3359592-1-jim.t90615@gmail.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-gpio@vger.kernel.org, openbmc@lists.ozlabs.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" This SGPIO controller is for NUVOTON NPCM7xx and NPCM8xx SoC. Nuvoton NPCM SGPIO module is combine serial to parallel IC (HC595) and parallel to serial IC (HC165), and use APB3 clock to control it. This interface has 4 pins (D_out , D_in, S_CLK, LDSH). NPCM7xx/NPCM8xx have two sgpio module each module can support up to 64 output pins,and up to 64 input pin, the pin is only for gpi or gpo. GPIO pins have sequential, First half is gpo and second half is gpi. Jim Liu (3): dt-bindings: gpio: add NPCM sgpio driver bindings arm: dts: nuvoton: npcm: Add sgpio feature gpio: nuvoton: Add Nuvoton NPCM sgpio driver .../bindings/gpio/nuvoton,sgpio.yaml | 86 +++ .../dts/nuvoton/nuvoton-common-npcm7xx.dtsi | 24 + drivers/gpio/Kconfig | 8 + drivers/gpio/Makefile | 1 + drivers/gpio/gpio-npcm-sgpio.c | 650 ++++++++++++++++++ 5 files changed, 769 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/nuvoton,sgpio.yaml create mode 100644 drivers/gpio/gpio-npcm-sgpio.c