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Sat, 29 Apr 2023 05:03:19 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=s31663417; t=1682708555; i=j.neuschaefer@gmx.net; bh=CF1sZz4k02QBYfgP0eXXL7Vnco7PO6Xo/WIy5gteZNg=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date; b=gxQGLql0UO32aR/fayGJyyJG34yeGaU3BgFp8KPOK9BuvAr4esK/8G+0dosUz0lDA GFC5CjWxzZz6CvelhNRw9G5NPAeiT+aafWjjNg0GeG5E8BeZmdgpQDrkhI9ppMgdjE wucdaF8MVTW4kWU/HAM00OhqBcxypUKyyev35jM9IlnQ9UIrW3TyMhg5foEtnJieCJ UN/KrjbQV+jV+QXpLNhfZrYP1ytO6Ht7RxjXUMTVmjko7U3Uhgt9iQ3S3TevXs/zGJ HfSz5TwZS/O3kB28S+SLovA8OfHlM/rWWOJFv+IoJwJH05+gtytdHcVQ8X4KB5KNx4 70tyK7f7YTAXA== X-UI-Sender-Class: 724b4f7f-cbec-4199-ad4e-598c01a50d3a Received: from probook ([87.78.41.149]) by mail.gmx.net (mrgmx005 [212.227.17.190]) with ESMTPSA (Nemesis) id 1Mzyya-1qE7Js3YIA-00x1DS; Fri, 28 Apr 2023 21:02:34 +0200 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-clk@vger.kernel.org, openbmc@lists.ozlabs.org Subject: [PATCH v8 0/2] Nuvoton WPCM450 clock and reset driver Date: Fri, 28 Apr 2023 21:02:24 +0200 Message-Id: <20230428190226.1304326-1-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 X-Provags-ID: V03:K1:wZTKlMlvr8MURaloy/YrVGLiLLZde8R5/fNsaUu9vm9S0L/O5Lo TWvjUFoxXbdneU/gfEioYGwkhrcBE39X2xRHtThROq5sjsoc98PqlfZCnPcYhTKPMUveSdA BZIduuv40QXtWWbQpDiVnVqnIExZzWmoIgu8oMScvX5v76dQNllRuZyL6cNegGJrXLvIsjI Hz00laEJ15UrvkwcKinVw== X-Spam-Flag: NO UI-OutboundReport: notjunk:1;M01:P0:hK/VS9yiUgg=;bXepyBgIkaLm4FvnsH2jSDzoNYo w7h+kaFOnKAFRI5yZVrczC8qfOVrfUcI0o1JhwH0UfoZNA60e8u63qJhldz8mnJpRtQub0IBe H2ajjZXGYSazTy18shkdIrZWVEQ8x83YEGZHW/tORAqKIAQE7dMBLdpnPZWij+/IndI1Zc8B4 dxWE8sQFz0KQjBuMVg+ZsLZJ+zDL7bdDZZk+gkcLNk3vzHVorA0/SAB5T3PKSFQlUf4YBZ7i7 BOnj0LRvSTlBnT5qJ6btIlbEiMrLRBXvqU1ROv2sgR2R/DukQK0vQ8YJBW+bl4h5jvOQb4TnI XRHqrnMeBeYusFpiaij+MQNxPyViDqxFagmjqFBP+/7F8hKqFv0850GNXZWUhiKNCiWPpi4z8 s/EQ0pklmMs86xj3ne+rGHRImDP4iQ3A+dFjwwrK59QLBZjFJBCMmdTG2S/cDzNS9cEL6hqVi rNhO6tdQPOcf1wYWxUiEbL8svYQmnIQHJQuZLARemNlFQrlSh6jxmAo8EB4cVUdh5aCpQ07RV SZRMgBytx2UlsXS1tC/otvqgHSf1595eS9SntJxf0Pi/QbKOSBzIzx/YsZVWVSM/5ZZx10Qi0 6pw1fDkfRtzpEE4GzR4MEMOJ/vb83aLDVjOphMIPFtx6yisKnvRe6iGNQt11saT97kgrO7edm 6E2AWvKsKiCb3ZUAao30/S33t1El8w+7upUoqlfeKv0b9M+Avy2Dfep3wuaVs1nFVFDSJN7AA KJ5Sgd5Et4RdmnmxCiUIdtOwDoD+YFI/Lgft6sWC/gZpxt+0MXkRwproXmnR+RsUaKlaVCyIb vS5rGI7fWdv9XRaV9C5UNDQR3HPjuPj2maJcK/9ejOXlhwLAsr2Lz8O1W4Jir0NmeUiflPRFa q5F8QdMgdztYg9ROW6BztI+vw5tnq+W34CB8KGxnOX8mDrAypfGSYnbMAMrkFcCfkc8XCT45i JjRs6MpNsi3aTqub4MY1Z+BZCQ0= X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Wim Van Sebroeck , linux-watchdog@vger.kernel.org, Stephen Boyd , Patrick Venture , Michael Turquette , Daniel Lezcano , linux-kernel@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Avi Fishman , Rob Herring , Christophe JAILLET , Benjamin Fair , Philipp Zabel , Krzysztof Kozlowski , Tali Perry , Thomas Gleixner , Guenter Roeck , Tomer Maimon Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" This series adds support for the clock and reset controller in the Nuvoton WPCM450 SoC. This means that the clock rates for peripherals will be calculated automatically based on the clock tree as it was preconfigured by the bootloader. The 24 MHz dummy clock, that is currently in the devicetree, is no longer needed. Somewhat unfortunately, this also means that there is a breaking change once the devicetree starts relying on the clock driver, but I find it acceptable in this case, because WPCM450 is still at a somewhat early stage. v8: - Use %pe throughout the driver v7: - Simplified the error handling, by largely removing resource deallocation, which: - was already incomplete - would only happen in a case when the system is in pretty bad state because the clock driver didn't initialize correctly (in other words, the clock driver isn't optional enough that complex error handling really pays off) v6: - Dropped all patches except the clock binding and the clock driver, because they have mostly been merged - Minor correction to how RESET_SIMPLE is selected v5: - Dropped patch 2 (watchdog: npcm: Enable clock if provided), which was since merged upstream - Added patch 2 (clocksource: timer-npcm7xx: Enable timer 1 clock before use) again, because I wasn't able to find it in linux-next - Switched the driver to using struct clk_parent_data - Rebased on 6.1-rc3 v4: - Leave WDT clock running during after restart handler - Fix reset controller initialization - Dropped patch 2/7 (clocksource: timer-npcm7xx: Enable timer 1 clock before use), as it was applied by Daniel Lezcano v3: - https://lore.kernel.org/lkml/20220508194333.2170161-1-j.neuschaefer@gmx.net/ - Changed "refclk" string to "ref" - Fixed some dead code in the driver - Added clk_prepare_enable call to the watchdog restart handler - Added a few review tags v2: - https://lore.kernel.org/lkml/20220429172030.398011-1-j.neuschaefer@gmx.net/ - various small improvements v1: - https://lore.kernel.org/lkml/20220422183012.444674-1-j.neuschaefer@gmx.net/ Jonathan Neuschäfer (2): dt-bindings: clock: Add Nuvoton WPCM450 clock/reset controller clk: wpcm450: Add Nuvoton WPCM450 clock/reset controller driver .../bindings/clock/nuvoton,wpcm450-clk.yaml | 66 ++++ drivers/clk/Makefile | 1 + drivers/clk/clk-wpcm450.c | 374 ++++++++++++++++++ drivers/reset/Kconfig | 2 +- .../dt-bindings/clock/nuvoton,wpcm450-clk.h | 67 ++++ 5 files changed, 509 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/clock/nuvoton,wpcm450-clk.yaml create mode 100644 drivers/clk/clk-wpcm450.c create mode 100644 include/dt-bindings/clock/nuvoton,wpcm450-clk.h --- 2.39.2