From patchwork Thu May 6 10:03:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Steven Lee X-Patchwork-Id: 1474892 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; envelope-from=openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FbTlc6kYpz9sW4 for ; Thu, 6 May 2021 20:07:24 +1000 (AEST) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4FbTlc6K7Tz30Mp for ; Thu, 6 May 2021 20:07:24 +1000 (AEST) X-Original-To: openbmc@lists.ozlabs.org Delivered-To: openbmc@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=fail (SPF fail - not authorized) smtp.mailfrom=aspeedtech.com (client-ip=211.20.114.71; helo=twspam01.aspeedtech.com; envelope-from=steven_lee@aspeedtech.com; receiver=) Received: from twspam01.aspeedtech.com (twspam01.aspeedtech.com [211.20.114.71]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4FbTlT3ML0z2yZB; Thu, 6 May 2021 20:07:16 +1000 (AEST) Received: from mail.aspeedtech.com ([192.168.0.24]) by twspam01.aspeedtech.com with ESMTP id 1469pPg0024628; Thu, 6 May 2021 17:51:25 +0800 (GMT-8) (envelope-from steven_lee@aspeedtech.com) Received: from localhost.localdomain (192.168.100.253) by TWMBX02.aspeed.com (192.168.0.24) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 6 May 2021 18:03:12 +0800 From: Steven Lee To: Andrew Jeffery , Ulf Hansson , Rob Herring , Joel Stanley , "Adrian Hunter" , Philipp Zabel , Ryan Chen , "moderated list:ASPEED SD/MMC DRIVER" , "moderated list:ASPEED SD/MMC DRIVER" , "open list:ASPEED SD/MMC DRIVER" , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "moderated list:ARM/ASPEED MACHINE SUPPORT" , open list Subject: [PATCH v3 0/5] mmc: sdhci-of-aspeed: Support toggling SD bus signal Date: Thu, 6 May 2021 18:03:07 +0800 Message-ID: <20210506100312.1638-1-steven_lee@aspeedtech.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-Originating-IP: [192.168.100.253] X-ClientProxiedBy: TWMBX02.aspeed.com (192.168.0.24) To TWMBX02.aspeed.com (192.168.0.24) X-DNSRBL: X-MAIL: twspam01.aspeedtech.com 1469pPg0024628 X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ryan_chen@aspeedtech.com, chin-ting_kuo@aspeedtech.com, steven_lee@aspeedtech.com, Hongweiz@ami.com Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" AST2600-A2 EVB has the reference design for enabling SD bus power and toggling SD bus signal voltage between 3.3v and 1.8v by GPIO regulators. This patch series provides the example for enabling regulators and supporting SDR104 mode on AST2600-A2 EVB. The description of the reference design of AST2600-A2 EVB is added in the dts file. This patch also include a helper for updating AST2600 sdhci capability registers, and assert/deassert the reset signal for cleaning up AST2600 eMMC controller before eMMC is probed. Changes from v2: * Move the comment of the reference design from dt-bindings to device tree. * Add clk-phase binding for eMMC controller. * Reimplement aspeed_sdc_set_slot_capability(). * Separate the implementation of eMMC reset to another patch file. * Fix yaml document error per the report of dt_binding_check and dtbs_check. Changes from v1: * Add the device tree example for AST2600 A2 EVB in dt-bindings document * Add timing-phase for eMMC controller. * Remove power-gpio and power-switch-gpio from sdhci driver, they should be handled by regulator. * Add a helper to update capability registers in the driver. * Sync sdhci settings from device tree to SoC capability registers. * Sync timing-phase from device tree to SoC Clock Phase Control register Please help to review. Regards, Steven Steven Lee (5): dt-bindings: mmc: sdhci-of-aspeed: Add an example for AST2600-A2 EVB ARM: dts: aspeed: ast2600evb: Add comment for gpio regulator of sdhci ARM: dts: aspeed: ast2600evb: Add phase correction for emmc controller. mmc: sdhci-of-aspeed: Add a helper for updating capability register. mmc: sdhci-of-aspeed: Assert/Deassert reset signal before probing eMMC .../devicetree/bindings/mmc/aspeed,sdhci.yaml | 101 ++++++++++++++++- arch/arm/boot/dts/aspeed-ast2600-evb.dts | 18 ++- drivers/mmc/host/sdhci-of-aspeed.c | 106 ++++++++++++++++-- 3 files changed, 211 insertions(+), 14 deletions(-)