From patchwork Wed Aug 19 21:42:28 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roland Dreier X-Patchwork-Id: 31672 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@bilbo.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from ozlabs.org (ozlabs.org [203.10.76.45]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "mx.ozlabs.org", Issuer "CA Cert Signing Authority" (verified OK)) by bilbo.ozlabs.org (Postfix) with ESMTPS id C447AB6F2B for ; Thu, 20 Aug 2009 07:42:36 +1000 (EST) Received: by ozlabs.org (Postfix) id B5A73DDD0C; Thu, 20 Aug 2009 07:42:36 +1000 (EST) Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.176.167]) by ozlabs.org (Postfix) with ESMTP id 0FAEEDDD0B for ; Thu, 20 Aug 2009 07:42:36 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753195AbZHSVm2 (ORCPT ); Wed, 19 Aug 2009 17:42:28 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1753182AbZHSVm2 (ORCPT ); Wed, 19 Aug 2009 17:42:28 -0400 Received: from sj-iport-1.cisco.com ([171.71.176.70]:38793 "EHLO sj-iport-1.cisco.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753101AbZHSVm1 (ORCPT ); Wed, 19 Aug 2009 17:42:27 -0400 X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: ApoEAIYOjEqrR7PE/2dsb2JhbAC9Y4gvkVwFhBqBUw X-IronPort-AV: E=Sophos;i="4.43,410,1246838400"; d="scan'208";a="230234085" Received: from sj-dkim-4.cisco.com ([171.71.179.196]) by sj-iport-1.cisco.com with ESMTP; 19 Aug 2009 21:42:29 +0000 Received: from sj-core-2.cisco.com (sj-core-2.cisco.com [171.71.177.254]) by sj-dkim-4.cisco.com (8.12.11/8.12.11) with ESMTP id n7JLgTGM020338; Wed, 19 Aug 2009 14:42:29 -0700 Received: from xbh-sjc-211.amer.cisco.com (xbh-sjc-211.cisco.com [171.70.151.144]) by sj-core-2.cisco.com (8.13.8/8.14.3) with ESMTP id n7JLgTHR015763; Wed, 19 Aug 2009 21:42:29 GMT Received: from xfe-sjc-212.amer.cisco.com ([171.70.151.187]) by xbh-sjc-211.amer.cisco.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 19 Aug 2009 14:42:28 -0700 Received: from roland-conroe ([10.33.42.9]) by xfe-sjc-212.amer.cisco.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 19 Aug 2009 14:42:28 -0700 Received: by roland-conroe (Postfix, from userid 33217) id 3E7E1E71D7; Wed, 19 Aug 2009 14:42:28 -0700 (PDT) From: Roland Dreier To: Christoph Lameter Cc: netdev@vger.kernel.org, Yevgeny Petrilin Subject: Re: mlx4 2.6.31-rc5: SW2HW_EQ failed. References: X-Message-Flag: Warning: May contain useful information Date: Wed, 19 Aug 2009 14:42:28 -0700 In-Reply-To: (Christoph Lameter's message of "Wed, 19 Aug 2009 11:47:36 -0400 (EDT)") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/23.0.91 (gnu/linux) MIME-Version: 1.0 X-OriginalArrivalTime: 19 Aug 2009 21:42:28.0574 (UTC) FILETIME=[F2D7CFE0:01CA2115] DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; l=5196; t=1250718149; x=1251582149; c=relaxed/simple; s=sjdkim4002; h=Content-Type:From:Subject:Content-Transfer-Encoding:MIME-Version; d=cisco.com; i=rdreier@cisco.com; z=From:=20Roland=20Dreier=20 |Subject:=20Re=3A=20mlx4=202.6.31-rc5=3A=20SW2HW_EQ=20faile d. |Sender:=20; bh=NyRPo595FRXrFZVhSagYCm108FPlj9gzIalWsbctygk=; b=HaDJOhrbO8+G6L39RwlpWYsFN6GeUoCRNR8sOUxwCPP9ctP0F+Hf7YWSA8 O7Sw70+37V5fKHHr8wFY5mvSer5pfz4iBWmNSOe6IT7RmgiAZxlOvlaP9ZpL gwO7lm3WO6; Authentication-Results: sj-dkim-4; header.From=rdreier@cisco.com; dkim=pass ( sig from cisco.com/sjdkim4002 verified; ); Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org I took another look at the patch I sent and found a couple of bugs in it (seems original authors didn't really test on a system with 32 CPUs). Anyway the patch below seems to work on a test system with 32 possible CPUs (including unloading). Let me know how it works for you. Thanks, Roland commit 75e8522a04e982623d67b959d2e545974f36c323 Author: Eli Cohen Date: Wed Aug 19 14:15:59 2009 -0700 mlx4_core: Allocate and map sufficient ICM memory for EQ context The current implementation allocates a single host page for EQ context memory, which was OK when we only allocated a few EQs. However, since we now allocate an EQ for each CPU core, this patch removes the hard-coded limit and makes the allocation depend on EQ entry size and the number of required EQs. Signed-off-by: Eli Cohen Signed-off-by: Roland Dreier --- To unsubscribe from this list: send the line "unsubscribe netdev" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/net/mlx4/eq.c b/drivers/net/mlx4/eq.c index c11a052..fffe1ea 100644 --- a/drivers/net/mlx4/eq.c +++ b/drivers/net/mlx4/eq.c @@ -529,31 +529,46 @@ int mlx4_map_eq_icm(struct mlx4_dev *dev, u64 icm_virt) { struct mlx4_priv *priv = mlx4_priv(dev); int ret; + int host_pages; + unsigned off; - /* - * We assume that mapping one page is enough for the whole EQ - * context table. This is fine with all current HCAs, because - * we only use 32 EQs and each EQ uses 64 bytes of context - * memory, or 1 KB total. - */ + host_pages = PAGE_ALIGN(min_t(int, dev->caps.num_eqs, num_possible_cpus() + 1) * + dev->caps.eqc_entry_size) >> PAGE_SHIFT; + priv->eq_table.order = order_base_2(host_pages); priv->eq_table.icm_virt = icm_virt; - priv->eq_table.icm_page = alloc_page(GFP_HIGHUSER); - if (!priv->eq_table.icm_page) - return -ENOMEM; + priv->eq_table.icm_page = alloc_pages(GFP_HIGHUSER, priv->eq_table.order); + if (!priv->eq_table.icm_page) { + ret = -ENOMEM; + goto err; + } priv->eq_table.icm_dma = pci_map_page(dev->pdev, priv->eq_table.icm_page, 0, - PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); + PAGE_SIZE << priv->eq_table.order, + PCI_DMA_BIDIRECTIONAL); if (pci_dma_mapping_error(dev->pdev, priv->eq_table.icm_dma)) { - __free_page(priv->eq_table.icm_page); - return -ENOMEM; + ret = -ENOMEM; + goto err_free; } - ret = mlx4_MAP_ICM_page(dev, priv->eq_table.icm_dma, icm_virt); - if (ret) { - pci_unmap_page(dev->pdev, priv->eq_table.icm_dma, PAGE_SIZE, - PCI_DMA_BIDIRECTIONAL); - __free_page(priv->eq_table.icm_page); + for (off = 0; off < PAGE_SIZE << priv->eq_table.order; off += MLX4_ICM_PAGE_SIZE) { + ret = mlx4_MAP_ICM_page(dev, priv->eq_table.icm_dma + off, + icm_virt + off); + if (ret) + goto err_unmap; } + return 0; + +err_unmap: + if (off) + mlx4_UNMAP_ICM(dev, priv->eq_table.icm_virt, off / MLX4_ICM_PAGE_SIZE); + pci_unmap_page(dev->pdev, priv->eq_table.icm_dma, + PAGE_SIZE << priv->eq_table.order, + PCI_DMA_BIDIRECTIONAL); + +err_free: + __free_pages(priv->eq_table.icm_page, priv->eq_table.order); + +err: return ret; } @@ -561,10 +576,11 @@ void mlx4_unmap_eq_icm(struct mlx4_dev *dev) { struct mlx4_priv *priv = mlx4_priv(dev); - mlx4_UNMAP_ICM(dev, priv->eq_table.icm_virt, 1); - pci_unmap_page(dev->pdev, priv->eq_table.icm_dma, PAGE_SIZE, - PCI_DMA_BIDIRECTIONAL); - __free_page(priv->eq_table.icm_page); + mlx4_UNMAP_ICM(dev, priv->eq_table.icm_virt, + (PAGE_SIZE / MLX4_ICM_PAGE_SIZE) << priv->eq_table.order); + pci_unmap_page(dev->pdev, priv->eq_table.icm_dma, + PAGE_SIZE << priv->eq_table.order, PCI_DMA_BIDIRECTIONAL); + __free_pages(priv->eq_table.icm_page, priv->eq_table.order); } int mlx4_alloc_eq_table(struct mlx4_dev *dev) diff --git a/drivers/net/mlx4/main.c b/drivers/net/mlx4/main.c index 5c1afe0..474d1f3 100644 --- a/drivers/net/mlx4/main.c +++ b/drivers/net/mlx4/main.c @@ -207,6 +207,7 @@ static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) dev->caps.max_cqes = dev_cap->max_cq_sz - 1; dev->caps.reserved_cqs = dev_cap->reserved_cqs; dev->caps.reserved_eqs = dev_cap->reserved_eqs; + dev->caps.eqc_entry_size = dev_cap->eqc_entry_sz; dev->caps.mtts_per_seg = 1 << log_mtts_per_seg; dev->caps.reserved_mtts = DIV_ROUND_UP(dev_cap->reserved_mtts, dev->caps.mtts_per_seg); diff --git a/drivers/net/mlx4/mlx4.h b/drivers/net/mlx4/mlx4.h index 5bd79c2..34bcc11 100644 --- a/drivers/net/mlx4/mlx4.h +++ b/drivers/net/mlx4/mlx4.h @@ -210,6 +210,7 @@ struct mlx4_eq_table { dma_addr_t icm_dma; struct mlx4_icm_table cmpt_table; int have_irq; + int order; u8 inta_pin; }; diff --git a/include/linux/mlx4/device.h b/include/linux/mlx4/device.h index ce7cc6c..8923c9b 100644 --- a/include/linux/mlx4/device.h +++ b/include/linux/mlx4/device.h @@ -206,6 +206,7 @@ struct mlx4_caps { int max_cqes; int reserved_cqs; int num_eqs; + int eqc_entry_size; int reserved_eqs; int num_comp_vectors; int num_mpts;