Message ID | E1kDVMQ-0000jX-D8@rmk-PC.armlinux.org.uk |
---|---|
State | Changes Requested |
Delegated to: | David Miller |
Headers | show |
Series | Marvell PP2.2 PTP support | expand |
On Wed, Sep 02, 2020 at 05:11:46PM +0100, Russell King wrote: > Check the first level interrupt status registers to determine how to > further process the port interrupt. We will need this to know whether > to invoke the link status processing and/or the PTP processing for > both XLG and GMAC. As i said, i don't know this driver. Does the hardware actually have two MAC hardware blocks? One for 10Mbs->1G, and a second for > 1G? The comments and code seem to fit, so: Reviewed-by: Andrew Lunn <andrew@lunn.ch> Andrew
On Thu, Sep 03, 2020 at 03:24:14AM +0200, Andrew Lunn wrote: > On Wed, Sep 02, 2020 at 05:11:46PM +0100, Russell King wrote: > > Check the first level interrupt status registers to determine how to > > further process the port interrupt. We will need this to know whether > > to invoke the link status processing and/or the PTP processing for > > both XLG and GMAC. > > As i said, i don't know this driver. Does the hardware actually have > two MAC hardware blocks? One for 10Mbs->1G, and a second for > 1G? Yes.
diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h index a2f787c83756..273c46bbf927 100644 --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h @@ -461,6 +461,8 @@ #define MVPP22_CTRL4_DP_CLK_SEL BIT(5) #define MVPP22_CTRL4_SYNC_BYPASS_DIS BIT(6) #define MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE BIT(7) +#define MVPP22_GMAC_INT_SUM_STAT 0xa0 +#define MVPP22_GMAC_INT_SUM_STAT_INTERNAL BIT(1) #define MVPP22_GMAC_INT_SUM_MASK 0xa4 #define MVPP22_GMAC_INT_SUM_MASK_LINK_STAT BIT(1) @@ -488,6 +490,8 @@ #define MVPP22_XLG_CTRL3_MACMODESELECT_MASK (7 << 13) #define MVPP22_XLG_CTRL3_MACMODESELECT_GMAC (0 << 13) #define MVPP22_XLG_CTRL3_MACMODESELECT_10G (1 << 13) +#define MVPP22_XLG_EXT_INT_STAT 0x158 +#define MVPP22_XLG_EXT_INT_STAT_XLG BIT(1) #define MVPP22_XLG_EXT_INT_MASK 0x15c #define MVPP22_XLG_EXT_INT_MASK_XLG BIT(1) #define MVPP22_XLG_EXT_INT_MASK_GIG BIT(2) diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c index 41ffae8d5357..9dc8cf3d0873 100644 --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c @@ -3039,14 +3039,23 @@ static void mvpp2_isr_handle_gmac_internal(struct mvpp2_port *port) static irqreturn_t mvpp2_port_isr(int irq, void *dev_id) { struct mvpp2_port *port = (struct mvpp2_port *)dev_id; + u32 val; mvpp22_gop_mask_irq(port); if (mvpp2_port_supports_xlg(port) && mvpp2_is_xlg(port->phy_interface)) { - mvpp2_isr_handle_xlg(port); + /* Check the external status register */ + val = readl(port->base + MVPP22_XLG_EXT_INT_STAT); + if (val & MVPP22_XLG_EXT_INT_STAT_XLG) + mvpp2_isr_handle_xlg(port); } else { - mvpp2_isr_handle_gmac_internal(port); + /* If it's not the XLG, we must be using the GMAC. + * Check the summary status. + */ + val = readl(port->base + MVPP22_GMAC_INT_SUM_STAT); + if (val & MVPP22_GMAC_INT_SUM_STAT_INTERNAL) + mvpp2_isr_handle_gmac_internal(port); } mvpp22_gop_unmask_irq(port);
Check the first level interrupt status registers to determine how to further process the port interrupt. We will need this to know whether to invoke the link status processing and/or the PTP processing for both XLG and GMAC. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> --- drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 4 ++++ drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 13 +++++++++++-- 2 files changed, 15 insertions(+), 2 deletions(-)