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Wed, 29 Apr 2020 09:03:33 +0000 Received: from CH2PR17MB3542.namprd17.prod.outlook.com ([fe80::684d:3302:3158:502c]) by CH2PR17MB3542.namprd17.prod.outlook.com ([fe80::684d:3302:3158:502c%5]) with mapi id 15.20.2937.023; Wed, 29 Apr 2020 09:03:33 +0000 From: "Badel, Laurent" To: "fugang.duan@nxp.com" , "netdev@vger.kernel.org" , "andrew@lunn.ch" , "f.fainelli@gmail.com" , "hkallweit1@gmail.com" , "linux@armlinux.org.uk" , "richard.leitner@skidata.com" , "davem@davemloft.net" , "alexander.levin@microsoft.com" , "gregkh@linuxfoundation.org" CC: "Quette, Arnaud" Subject: [PATCH 1/2] Revert commit 1b0a83ac04e383e3bed21332962b90710fcf2828 Thread-Topic: [PATCH 1/2] Revert commit 1b0a83ac04e383e3bed21332962b90710fcf2828 Thread-Index: AdYeA4i+jkYua/a0S76wXm6HsC2C+Q== Date: Wed, 29 Apr 2020 09:03:32 +0000 Message-ID: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: nxp.com; dkim=none (message not signed) header.d=none;nxp.com; dmarc=none action=none header.from=eaton.com; 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Rationale: the SMSC LAN8720 (and possibly other chips) is known to require a reset after the external clock is enabled. Calls to phy_reset_after_clk_enable() in fec_main.c have been introduced in commit 1b0a83ac04e3 ("net: fec: add phy_reset_after_clk_enable() support") to handle the chip reset after enabling the clock. However, this breaks when interrupts are enabled because the reset reverts the configuration of the PHY interrupt mask to default (in addition it also reverts the "energy detect" mode setting). As a result the driver does not receive the link status change and other notifications resulting in loss of connectivity. Proposed solution: revert commit 1b0a83ac04e3 and bring the reset before the PHY configuration by adding it to phy_init_hw() [phy_device.c]. Test results: using an iMX28-EVK-based board, these 2 patches successfully restore network interface functionality when interrupts are enabled. Tested using both linux-5.4.23 and latest mainline (5.6.0) kernels. Fixes: 1b0a83ac04e383e3bed21332962b90710fcf2828 ("net: fec: add phy_reset_after_clk_enable() support") Signed-off-by: Laurent Badel --- drivers/net/ethernet/freescale/fec_main.c | 19 ------------------- 1 file changed, 19 deletions(-) diff --git a/drivers/net/ethernet/freescale/fec_main.c b/drivers/net/ethernet/freescale/fec_main.c index 23c5fef2f..02b014837 100644 --- a/drivers/net/ethernet/freescale/fec_main.c +++ b/drivers/net/ethernet/freescale/fec_main.c @@ -1918,7 +1918,6 @@ static int fec_enet_clk_enable(struct net_device *ndev, bool enable) if (ret) goto failed_clk_ref; - phy_reset_after_clk_enable(ndev->phydev); } else { clk_disable_unprepare(fep->clk_enet_out); if (fep->clk_ptp) { @@ -2895,7 +2894,6 @@ fec_enet_open(struct net_device *ndev) { struct fec_enet_private *fep = netdev_priv(ndev); int ret; - bool reset_again; ret = pm_runtime_get_sync(&fep->pdev->dev); if (ret < 0) @@ -2906,17 +2904,6 @@ fec_enet_open(struct net_device *ndev) if (ret) goto clk_enable; - /* During the first fec_enet_open call the PHY isn't probed at this - * point. Therefore the phy_reset_after_clk_enable() call within - * fec_enet_clk_enable() fails. As we need this reset in order to be - * sure the PHY is working correctly we check if we need to reset again - * later when the PHY is probed - */ - if (ndev->phydev && ndev->phydev->drv) - reset_again = false; - else - reset_again = true; - /* I should reset the ring buffers here, but I don't yet know * a simple way to do that. */ @@ -2933,12 +2920,6 @@ fec_enet_open(struct net_device *ndev) if (ret) goto err_enet_mii_probe; - /* Call phy_reset_after_clk_enable() again if it failed during - * phy_reset_after_clk_enable() before because the PHY wasn't probed. - */ - if (reset_again) - phy_reset_after_clk_enable(ndev->phydev); - if (fep->quirks & FEC_QUIRK_ERR006687) imx6q_cpuidle_fec_irqs_used();