From patchwork Sun Jan 22 19:18:21 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergei Shtylyov X-Patchwork-Id: 718263 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3v643p01x6z9svs for ; Mon, 23 Jan 2017 06:18:30 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=cogentembedded-com.20150623.gappssmtp.com header.i=@cogentembedded-com.20150623.gappssmtp.com header.b="HSdcNBK8"; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751491AbdAVTS2 (ORCPT ); Sun, 22 Jan 2017 14:18:28 -0500 Received: from mail-lf0-f47.google.com ([209.85.215.47]:33859 "EHLO mail-lf0-f47.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751337AbdAVTS0 (ORCPT ); Sun, 22 Jan 2017 14:18:26 -0500 Received: by mail-lf0-f47.google.com with SMTP id v186so83514224lfa.1 for ; Sun, 22 Jan 2017 11:18:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cogentembedded-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:organization:user-agent :in-reply-to:references:mime-version:content-transfer-encoding; bh=BfKk6gIUwSWVx55N/poNRjLnWGKjgOJlDZZbSxIiTZk=; b=HSdcNBK844PC9Ohld71gVa6Z6/dY3UpWZ5UlNq9wTFQeKdZyqK6a46cTQl6WNMP0SC ySqiIqwtGQCqOccFdFNmPqGDlvW9DlKExwEoGtIk7KUjYBAwy8KkhtzqUNYeOYC/Wopj lQ09KkcY4x5Nq0pr5ji5PlssrOeK7ku3yHmFfgn7n96NVKJN9hvDcw8awknDpUtEu99d WfJOqhl3DWkb3vG8+RI+3A9tSi4+SXyl94Ax7spaM0vvxitASnKtOaY3xXhKSQk7YER+ btpkYtFzAujONzIMLqmM3TCcJtV67bB8uZ+UA3L4sxQ1VCqu1i7UVaoO/DxAsX/7f1cB oP5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:organization :user-agent:in-reply-to:references:mime-version :content-transfer-encoding; bh=BfKk6gIUwSWVx55N/poNRjLnWGKjgOJlDZZbSxIiTZk=; b=br6y2+YooPvqkFk2cJKc7j01+nSO0pjB/5p/a9j2qE6lpkDpx8lngQ8OzkJTOfHaAH b+/MWM7ma4pedam3sK+6fBL26uzIri07Ah/OoqmU/8HDikiPu37fjZchEkaHSuk8oeV7 Y+Q4IR2iz+8EUso6NTKT4g/waxvs6vgqxprke3oDd1nnzxUe2ZyN+EEzDzc2Mv7aEiZ/ rNQax/TOIUTWfRT38qCSP30wR+J8jvy2dGcsWfaXiULBScTv2Z+hMh07etvd/8aPagvh mcbSaYGYmuFalxbZlC2W4oK4hi6Kz9LyrKViBsMD9db8TKoWk1JFxSt2yrdEmLS27uWb HlLA== X-Gm-Message-State: AIkVDXKs0lwMTFzLivSBVBw6MrxBPIdK4bVpishyRbEQwUQ4FGeyng8mdvVB1nIX0SiUeQ== X-Received: by 10.46.7.18 with SMTP id 18mr10107590ljh.62.1485112704072; Sun, 22 Jan 2017 11:18:24 -0800 (PST) Received: from wasted.cogentembedded.com ([31.173.81.46]) by smtp.gmail.com with ESMTPSA id y21sm1406819lfj.19.2017.01.22.11.18.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 22 Jan 2017 11:18:23 -0800 (PST) From: Sergei Shtylyov To: netdev@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org Subject: [PATCH 1/3] sh_eth: rename EESIPR bits Date: Sun, 22 Jan 2017 22:18:21 +0300 Message-ID: <6851530.HAKW22qnWH@wasted.cogentembedded.com> Organization: Cogent Embedded Inc. User-Agent: KMail/4.14.10 (Linux/4.8.13-100.fc23.x86_64; KDE/4.14.20; x86_64; ; ) In-Reply-To: <1636105.gp4aQxGd5K@wasted.cogentembedded.com> References: <1636105.gp4aQxGd5K@wasted.cogentembedded.com> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Since the commit b0ca2a21f769 ("sh_eth: Add support of SH7763 to sh_eth") the *enum* declaring the EESIPR bits (interrupt mask) went out of sync with the *enum* declaring the EESR bits (interrupt status) WRT bit naming and formatting. I'd like to restore the consistency by using EESIPR as the bit name prefix, renaming the *enum* to EESIPR_BIT, and (finally) renaming the bits according to the available Renesas SH77{34|63} manuals... Signed-off-by: Sergei Shtylyov --- drivers/net/ethernet/renesas/sh_eth.c | 22 ++++++++++---------- drivers/net/ethernet/renesas/sh_eth.h | 36 +++++++++++++++++++++------------- 2 files changed, 34 insertions(+), 24 deletions(-) Index: net-next/drivers/net/ethernet/renesas/sh_eth.c =================================================================== --- net-next.orig/drivers/net/ethernet/renesas/sh_eth.c +++ net-next/drivers/net/ethernet/renesas/sh_eth.c @@ -556,7 +556,7 @@ static struct sh_eth_cpu_data r8a7740_da .ecsr_value = ECSR_ICD | ECSR_MPD, .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, - .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, + .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 0x003fffff, .tx_check = EESR_TC1 | EESR_FTC, .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | @@ -702,7 +702,7 @@ static struct sh_eth_cpu_data sh7757_dat .register_type = SH_ETH_REG_FAST_SH4, - .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, + .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 0x003fffff, .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | @@ -769,7 +769,7 @@ static struct sh_eth_cpu_data sh7757_dat .ecsr_value = ECSR_ICD | ECSR_MPD, .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, - .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, + .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 0x003fffff, .tx_check = EESR_TC1 | EESR_FTC, .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | @@ -800,7 +800,7 @@ static struct sh_eth_cpu_data sh7734_dat .ecsr_value = ECSR_ICD | ECSR_MPD, .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, - .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003f07ff, + .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 0x003f07ff, .tx_check = EESR_TC1 | EESR_FTC, .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | @@ -830,7 +830,7 @@ static struct sh_eth_cpu_data sh7763_dat .ecsr_value = ECSR_ICD | ECSR_MPD, .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, - .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003f07ff, + .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 0x003f07ff, .tx_check = EESR_TC1 | EESR_FTC, .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | @@ -851,7 +851,7 @@ static struct sh_eth_cpu_data sh7763_dat static struct sh_eth_cpu_data sh7619_data = { .register_type = SH_ETH_REG_FAST_SH3_SH2, - .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, + .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 0x003fffff, .apr = 1, .mpr = 1, @@ -862,7 +862,7 @@ static struct sh_eth_cpu_data sh7619_dat static struct sh_eth_cpu_data sh771x_data = { .register_type = SH_ETH_REG_FAST_SH3_SH2, - .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, + .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 0x003fffff, .tsu = 1, }; @@ -1547,10 +1547,10 @@ static void sh_eth_emac_interrupt(struct sh_eth_rcv_snd_disable(ndev); } else { /* Link Up */ - sh_eth_modify(ndev, EESIPR, DMAC_M_ECI, 0); + sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, 0); /* clear int */ sh_eth_modify(ndev, ECSR, 0, 0); - sh_eth_modify(ndev, EESIPR, DMAC_M_ECI, DMAC_M_ECI); + sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, EESIPR_ECIIP); /* enable tx and rx */ sh_eth_rcv_snd_enable(ndev); } @@ -1652,7 +1652,7 @@ static irqreturn_t sh_eth_interrupt(int * bit... */ intr_enable = sh_eth_read(ndev, EESIPR); - intr_status &= intr_enable | DMAC_M_ECI; + intr_status &= intr_enable | EESIPR_ECIIP; if (intr_status & (EESR_RX_CHECK | cd->tx_check | EESR_ECI | cd->eesr_err_check)) ret = IRQ_HANDLED; @@ -3199,7 +3199,7 @@ static int sh_eth_wol_setup(struct net_d /* Only allow ECI interrupts */ synchronize_irq(ndev->irq); napi_disable(&mdp->napi); - sh_eth_write(ndev, DMAC_M_ECI, EESIPR); + sh_eth_write(ndev, EESIPR_ECIIP, EESIPR); /* Enable MagicPacket */ sh_eth_modify(ndev, ECMR, 0, ECMR_MPDE); Index: net-next/drivers/net/ethernet/renesas/sh_eth.h =================================================================== --- net-next.orig/drivers/net/ethernet/renesas/sh_eth.h +++ net-next/drivers/net/ethernet/renesas/sh_eth.h @@ -268,19 +268,29 @@ enum EESR_BIT { EESR_TFE | EESR_TDE) /* EESIPR */ -enum DMAC_IM_BIT { - DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000, - DMAC_M_RABT = 0x02000000, - DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000, - DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000, - DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000, - DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000, - DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800, - DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200, - DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080, - DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008, - DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002, - DMAC_M_RINT1 = 0x00000001, +enum EESIPR_BIT { + EESIPR_TWBIP = 0x40000000, + EESIPR_TABTIP = 0x04000000, + EESIPR_RABTIP = 0x02000000, + EESIPR_RFCOFIP = 0x01000000, + EESIPR_ADEIP = 0x00800000, + EESIPR_ECIIP = 0x00400000, + EESIPR_FTCIP = 0x00200000, + EESIPR_TDEIP = 0x00100000, + EESIPR_TFUFIP = 0x00080000, + EESIPR_FRIP = 0x00040000, + EESIPR_RDEIP = 0x00020000, + EESIPR_RFOFIP = 0x00010000, + EESIPR_CNDIP = 0x00000800, + EESIPR_DLCIP = 0x00000400, + EESIPR_CDIP = 0x00000200, + EESIPR_TROIP = 0x00000100, + EESIPR_RMAFIP = 0x00000080, + EESIPR_RRFIP = 0x00000010, + EESIPR_RTLFIP = 0x00000008, + EESIPR_RTSFIP = 0x00000004, + EESIPR_PREIP = 0x00000002, + EESIPR_CERFIP = 0x00000001, }; /* Receive descriptor 0 bits */