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[178.255.168.35]) by smtp.gmail.com with ESMTPSA id b195sm11133077wmf.38.2017.08.07.06.47.59 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Mon, 07 Aug 2017 06:47:59 -0700 (PDT) From: Michal Simek To: linux-kernel@vger.kernel.org, monstr@monstr.eu Cc: Andrea Scian , =?UTF-8?q?S=C3=B6ren=20Brinkmann?= , netdev@vger.kernel.org, Marc Kleine-Budde , linux-can@vger.kernel.org, Wolfgang Grandegger , linux-arm-kernel@lists.infradead.org Subject: [PATCH 2/2] can: xilinx: fix RX FIFO overflow error handling Date: Mon, 7 Aug 2017 15:47:57 +0200 Message-Id: <67efa4531bb8b83d5539c0bc0af32a9c9a523627.1502113674.git.michal.simek@xilinx.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <21850c76207942f5ae5c225f2627fb068d5234d0.1502113674.git.michal.simek@xilinx.com> References: <21850c76207942f5ae5c225f2627fb068d5234d0.1502113674.git.michal.simek@xilinx.com> In-Reply-To: <21850c76207942f5ae5c225f2627fb068d5234d0.1502113674.git.michal.simek@xilinx.com> References: <21850c76207942f5ae5c225f2627fb068d5234d0.1502113674.git.michal.simek@xilinx.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Andrea Scian Simply resetting the peripheral on RX FIFO overflow in not enough, because we also need to re-initialize the whole device. Also always enable RX FIFO overflow interrupt otherwise we may hang until another interrupt arrives (this happens if FIFO overrun and just read from CAN bus with candump) Signed-off-by: Andrea Scian Reviewed-by: Kedareswara rao Appana Signed-off-by: Michal Simek --- drivers/net/can/xilinx_can.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/net/can/xilinx_can.c b/drivers/net/can/xilinx_can.c index 05ea2820d27b..2c119d16861e 100644 --- a/drivers/net/can/xilinx_can.c +++ b/drivers/net/can/xilinx_can.c @@ -101,6 +101,7 @@ enum xcan_reg { #define XCAN_INTR_ALL (XCAN_IXR_TXOK_MASK | XCAN_IXR_BSOFF_MASK |\ XCAN_IXR_WKUP_MASK | XCAN_IXR_SLP_MASK | \ XCAN_IXR_RXNEMP_MASK | XCAN_IXR_ERROR_MASK | \ + XCAN_IXR_RXOFLW_MASK | \ XCAN_IXR_ARBLST_MASK) /* CAN register bit shift - XCAN___SHIFT */ @@ -529,6 +530,8 @@ static int xcan_rx(struct net_device *ndev) return 1; } +static void xcan_chip_stop(struct net_device *ndev); + /** * xcan_err_interrupt - error frame Isr * @ndev: net_device pointer @@ -600,7 +603,8 @@ static void xcan_err_interrupt(struct net_device *ndev, u32 isr) if (isr & XCAN_IXR_RXOFLW_MASK) { stats->rx_over_errors++; stats->rx_errors++; - priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK); + xcan_chip_stop(ndev); + xcan_chip_start(ndev); if (skb) { cf->can_id |= CAN_ERR_CRTL; cf->data[1] |= CAN_ERR_CRTL_RX_OVERFLOW;