From patchwork Wed Apr 17 07:33:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jose Abreu X-Patchwork-Id: 1086827 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=synopsys.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=synopsys.com header.i=@synopsys.com header.b="W3aA2C88"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44kZ4N4W4Nz9s71 for ; Wed, 17 Apr 2019 17:44:04 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730488AbfDQHnv (ORCPT ); Wed, 17 Apr 2019 03:43:51 -0400 Received: from dc2-smtprelay2.synopsys.com ([198.182.61.142]:46338 "EHLO smtprelay-out1.synopsys.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727447AbfDQHnu (ORCPT ); Wed, 17 Apr 2019 03:43:50 -0400 Received: from mailhost1.synopsys.com (us02-dmz-cl-eth-s1p4c0.internal.synopsys.com [10.12.241.126]) by smtprelay-out1.synopsys.com (Postfix) with ESMTP id 907F8C0B14; Wed, 17 Apr 2019 07:33:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=synopsys.com; s=mail; t=1555486394; bh=fg7z+hdIYKWaMyHO2cSI1s6q90ANqnyzXocHfWI4dKQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:In-Reply-To: References:From; b=W3aA2C88qhWd6xAHpCUa8o3MnjR2F9VT/knoDG1+IQNu5wkuzs2Cco5YmauphtkNT ZCC2/+mX0GqLY1tBzHPKpC8xLZRNRF1kOxCjn7bK1hENTXYYFZymKmUP8ehXq2Nixo uip2u/MD2cT17vo+2pzbdbDUPJTVvUI/1cGZl2rNO61YQWE+vuKiqgbd9mFLjUmL6k bPiwIm5mijcllx7y/0+J4GzNUc8UpIx8Cj/8739fwech/Z5kyLyXzjcFv2ekNjJoaT TQ9MgFoUoNObNtWfAbd6NdjjEWhB/0Fn9j3XqOpvkt3fNpa2+rDgF/RziOfsXxBhXi 9NeTRMj7Xx5PQ== Received: from de02dwia024.internal.synopsys.com (de02dwia024.internal.synopsys.com [10.225.19.81]) by mailhost1.synopsys.com (Postfix) with ESMTP id 44495501C; Wed, 17 Apr 2019 00:33:13 -0700 (PDT) From: Jose Abreu To: netdev@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Jose Abreu , Joao Pinto , "David S . Miller" , Giuseppe Cavallaro , Alexandre Torgue Subject: [PATCH net-next 1/2] net: stmmac: dwxgmac: Finish the Flow Control implementation Date: Wed, 17 Apr 2019 09:33:04 +0200 Message-Id: <6025da4fc4390316adf2abb32f4afcea2b4aef35.1555486210.git.joabreu@synopsys.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: In-Reply-To: References: Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Finish the implementation of Flow Control feature. In order for it to work correctly we need to set EHFC bit and the correct threshold values for activating and deactivating it. Signed-off-by: Jose Abreu Cc: Joao Pinto Cc: David S. Miller Cc: Giuseppe Cavallaro Cc: Alexandre Torgue --- drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h | 5 +++ drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c | 46 ++++++++++++++++++++++ 2 files changed, 51 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h index 37d5e6fe7473..085b700a4994 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h @@ -143,6 +143,11 @@ #define XGMAC_RSF BIT(5) #define XGMAC_RTC GENMASK(1, 0) #define XGMAC_RTC_SHIFT 0 +#define XGMAC_MTL_RXQ_FLOW_CONTROL(x) (0x00001150 + (0x80 * (x))) +#define XGMAC_RFD GENMASK(31, 17) +#define XGMAC_RFD_SHIFT 17 +#define XGMAC_RFA GENMASK(15, 1) +#define XGMAC_RFA_SHIFT 1 #define XGMAC_MTL_QINTEN(x) (0x00001170 + (0x80 * (x))) #define XGMAC_RXOIE BIT(16) #define XGMAC_MTL_QINT_STATUS(x) (0x00001174 + (0x80 * (x))) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c index 2ba712b48a89..e79037f511e1 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c @@ -147,6 +147,52 @@ static void dwxgmac2_dma_rx_mode(void __iomem *ioaddr, int mode, value &= ~XGMAC_RQS; value |= (rqs << XGMAC_RQS_SHIFT) & XGMAC_RQS; + if ((fifosz >= 4096) && (qmode != MTL_QUEUE_AVB)) { + u32 flow = readl(ioaddr + XGMAC_MTL_RXQ_FLOW_CONTROL(channel)); + unsigned int rfd, rfa; + + value |= XGMAC_EHFC; + + /* Set Threshold for Activating Flow Control to min 2 frames, + * i.e. 1500 * 2 = 3000 bytes. + * + * Set Threshold for Deactivating Flow Control to min 1 frame, + * i.e. 1500 bytes. + */ + switch (fifosz) { + case 4096: + /* This violates the above formula because of FIFO size + * limit therefore overflow may occur in spite of this. + */ + rfd = 0x03; /* Full-2.5K */ + rfa = 0x01; /* Full-1.5K */ + break; + + case 8192: + rfd = 0x06; /* Full-4K */ + rfa = 0x0a; /* Full-6K */ + break; + + case 16384: + rfd = 0x06; /* Full-4K */ + rfa = 0x12; /* Full-10K */ + break; + + default: + rfd = 0x06; /* Full-4K */ + rfa = 0x1e; /* Full-16K */ + break; + } + + flow &= ~XGMAC_RFD; + flow |= rfd << XGMAC_RFD_SHIFT; + + flow &= ~XGMAC_RFA; + flow |= rfa << XGMAC_RFA_SHIFT; + + writel(flow, ioaddr + XGMAC_MTL_RXQ_FLOW_CONTROL(channel)); + } + writel(value, ioaddr + XGMAC_MTL_RXQ_OPMODE(channel)); /* Enable MTL RX overflow */