From patchwork Thu Feb 23 13:34:05 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yevgeny Petrilin X-Patchwork-Id: 142612 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 78274B6EE8 for ; Fri, 24 Feb 2012 00:34:13 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754114Ab2BWNeL (ORCPT ); Thu, 23 Feb 2012 08:34:11 -0500 Received: from eu1sys200aog112.obsmtp.com ([207.126.144.133]:35377 "HELO eu1sys200aog112.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with SMTP id S1754115Ab2BWNeK (ORCPT ); Thu, 23 Feb 2012 08:34:10 -0500 Received: from MTLCAS01.mtl.com ([194.90.237.34]) (using TLSv1) by eu1sys200aob112.postini.com ([207.126.147.11]) with SMTP ID DSNKT0ZATnU24CsaHC9JiusGf5fLiB0o2562@postini.com; Thu, 23 Feb 2012 13:34:09 UTC Received: from [10.4.45.17] (10.0.13.1) by MTLCAS01.mtl.com (10.0.8.71) with Microsoft SMTP Server id 14.2.247.3; Thu, 23 Feb 2012 15:34:05 +0200 Message-ID: <4F46404D.10509@mellanox.co.il> Date: Thu, 23 Feb 2012 15:34:05 +0200 From: Yevgeny Petrilin User-Agent: Thunderbird 2.0.0.17 (X11/20080914) MIME-Version: 1.0 To: CC: , Subject: [PATCH net-next 1/3] mlx4_en: TX ring size default to 1024 X-Originating-IP: [10.0.13.1] Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Signed-off-by: Yevgeny Petrilin --- drivers/net/ethernet/mellanox/mlx4/mlx4_en.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx4/mlx4_en.h b/drivers/net/ethernet/mellanox/mlx4/mlx4_en.h index d60335f..174dc38 100644 --- a/drivers/net/ethernet/mellanox/mlx4/mlx4_en.h +++ b/drivers/net/ethernet/mellanox/mlx4/mlx4_en.h @@ -110,7 +110,7 @@ enum { #define MLX4_EN_NUM_TX_RINGS 8 #define MLX4_EN_NUM_PPP_RINGS 8 #define MAX_TX_RINGS (MLX4_EN_NUM_TX_RINGS + MLX4_EN_NUM_PPP_RINGS) -#define MLX4_EN_DEF_TX_RING_SIZE 512 +#define MLX4_EN_DEF_TX_RING_SIZE 1024 #define MLX4_EN_DEF_RX_RING_SIZE 1024 /* Target number of packets to coalesce with interrupt moderation */