From patchwork Thu Sep 12 07:05:11 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 274446 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 12F1A2C0396 for ; Thu, 12 Sep 2013 17:05:50 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756169Ab3ILHFe (ORCPT ); Thu, 12 Sep 2013 03:05:34 -0400 Received: from mail-ea0-f182.google.com ([209.85.215.182]:56885 "EHLO mail-ea0-f182.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755236Ab3ILHFQ (ORCPT ); Thu, 12 Sep 2013 03:05:16 -0400 Received: by mail-ea0-f182.google.com with SMTP id o10so5054489eaj.41 for ; Thu, 12 Sep 2013 00:05:15 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:in-reply-to:references:content-type; bh=8Kd3t6zx+jewRm6cMV38kjxm2ykN0f+nafZiCCf8iAc=; b=FLxMs7rnSEtE5jhyurVrC7t+eCc+nnFKZ6zKV2KbnErO4t52vwGJKTjwgVnC0ZZ4Qm gwXjrKxl7ign2czg6msqLt9QSiXoG+mYP+FdNaGe9N2cbNW/5P4WhhOIFdeoamu+oOyD sL0Olr4EjHVoTv8pbSiQNYtBTWpFzr78UgaCfD4R/VWTE0gx8U2Al/L3RPTUGxRoYQpz DwebrTi0leZTa+JhgoflKr3Dv3EKBZX0sABAZ4MlFdzIrP5JFaxeHsopDAp+njD/iNTw DrWxo6gGgPtK+dEAfmQxqFlW9W6EmeO2mdy0mGUn2rororfV6cjuhBPCTqiwcnEqYIoj DzHw== X-Gm-Message-State: ALoCoQma5X3cAkYNV3IA5v+2z5X3hqzfNC/7zXRLeELLvy67p+groV37EM8dbb60qU+XNTmEYDwS X-Received: by 10.14.175.2 with SMTP id y2mr24205eel.83.1378969515328; Thu, 12 Sep 2013 00:05:15 -0700 (PDT) Received: from localhost (nat-63.starnet.cz. [178.255.168.63]) by mx.google.com with ESMTPSA id y47sm3179688eew.12.1969.12.31.16.00.00 (version=TLSv1.1 cipher=RC4-SHA bits=128/128); Thu, 12 Sep 2013 00:05:14 -0700 (PDT) From: Michal Simek To: netdev@vger.kernel.org Cc: Michal Simek , "David S. Miller" , Jens Renner , Libo Chen , Greg Kroah-Hartman , linux-kernel@vger.kernel.org Subject: [PATCH 2/2] net: emaclite: Code cleanup Date: Thu, 12 Sep 2013 09:05:11 +0200 Message-Id: <22c8762e2e6eb8bb7d8b945b8f0a17f54e5c718c.1378969499.git.michal.simek@xilinx.com> X-Mailer: git-send-email 1.8.2.3 In-Reply-To: <196d8368eee2d45eeeab40e96e2971f78ed8a79b.1378969499.git.michal.simek@xilinx.com> References: <196d8368eee2d45eeeab40e96e2971f78ed8a79b.1378969499.git.michal.simek@xilinx.com> In-Reply-To: <196d8368eee2d45eeeab40e96e2971f78ed8a79b.1378969499.git.michal.simek@xilinx.com> References: <196d8368eee2d45eeeab40e96e2971f78ed8a79b.1378969499.git.michal.simek@xilinx.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org No function changes (s/\ \t/\t/g) Signed-off-by: Michal Simek --- drivers/net/ethernet/xilinx/xilinx_emaclite.c | 28 +++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) -- 1.8.2.3 diff --git a/drivers/net/ethernet/xilinx/xilinx_emaclite.c b/drivers/net/ethernet/xilinx/xilinx_emaclite.c index de39098..80dd404 100644 --- a/drivers/net/ethernet/xilinx/xilinx_emaclite.c +++ b/drivers/net/ethernet/xilinx/xilinx_emaclite.c @@ -31,7 +31,7 @@ #define DRIVER_NAME "xilinx_emaclite" /* Register offsets for the EmacLite Core */ -#define XEL_TXBUFF_OFFSET 0x0 /* Transmit Buffer */ +#define XEL_TXBUFF_OFFSET 0x0 /* Transmit Buffer */ #define XEL_MDIOADDR_OFFSET 0x07E4 /* MDIO Address Register */ #define XEL_MDIOWR_OFFSET 0x07E8 /* MDIO Write Data Register */ #define XEL_MDIORD_OFFSET 0x07EC /* MDIO Read Data Register */ @@ -63,13 +63,13 @@ #define XEL_MDIOCTRL_MDIOEN_MASK 0x00000008 /* MDIO Enable */ /* Global Interrupt Enable Register (GIER) Bit Masks */ -#define XEL_GIER_GIE_MASK 0x80000000 /* Global Enable */ +#define XEL_GIER_GIE_MASK 0x80000000 /* Global Enable */ /* Transmit Status Register (TSR) Bit Masks */ -#define XEL_TSR_XMIT_BUSY_MASK 0x00000001 /* Tx complete */ -#define XEL_TSR_PROGRAM_MASK 0x00000002 /* Program the MAC address */ -#define XEL_TSR_XMIT_IE_MASK 0x00000008 /* Tx interrupt enable bit */ -#define XEL_TSR_XMIT_ACTIVE_MASK 0x80000000 /* Buffer is active, SW bit +#define XEL_TSR_XMIT_BUSY_MASK 0x00000001 /* Tx complete */ +#define XEL_TSR_PROGRAM_MASK 0x00000002 /* Program the MAC address */ +#define XEL_TSR_XMIT_IE_MASK 0x00000008 /* Tx interrupt enable bit */ +#define XEL_TSR_XMIT_ACTIVE_MASK 0x80000000 /* Buffer is active, SW bit * only. This is not documented * in the HW spec */ @@ -77,21 +77,21 @@ #define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK) /* Receive Status Register (RSR) */ -#define XEL_RSR_RECV_DONE_MASK 0x00000001 /* Rx complete */ -#define XEL_RSR_RECV_IE_MASK 0x00000008 /* Rx interrupt enable bit */ +#define XEL_RSR_RECV_DONE_MASK 0x00000001 /* Rx complete */ +#define XEL_RSR_RECV_IE_MASK 0x00000008 /* Rx interrupt enable bit */ /* Transmit Packet Length Register (TPLR) */ -#define XEL_TPLR_LENGTH_MASK 0x0000FFFF /* Tx packet length */ +#define XEL_TPLR_LENGTH_MASK 0x0000FFFF /* Tx packet length */ /* Receive Packet Length Register (RPLR) */ -#define XEL_RPLR_LENGTH_MASK 0x0000FFFF /* Rx packet length */ +#define XEL_RPLR_LENGTH_MASK 0x0000FFFF /* Rx packet length */ -#define XEL_HEADER_OFFSET 12 /* Offset to length field */ -#define XEL_HEADER_SHIFT 16 /* Shift value for length */ +#define XEL_HEADER_OFFSET 12 /* Offset to length field */ +#define XEL_HEADER_SHIFT 16 /* Shift value for length */ /* General Ethernet Definitions */ -#define XEL_ARP_PACKET_SIZE 28 /* Max ARP packet size */ -#define XEL_HEADER_IP_LENGTH_OFFSET 16 /* IP Length Offset */ +#define XEL_ARP_PACKET_SIZE 28 /* Max ARP packet size */ +#define XEL_HEADER_IP_LENGTH_OFFSET 16 /* IP Length Offset */