| Message ID | 20200825120721.32746-1-daniel.gorsulowski@esd.eu |
|---|---|
| State | Changes Requested |
| Delegated to: | David Miller |
| Headers | show |
| Series | net: dp83869: Fix RGMII internal delay configuration | expand |
From: Daniel Gorsulowski <daniel.gorsulowski@esd.eu> Date: Tue, 25 Aug 2020 14:07:21 +0200 > The RGMII control register at 0x32 indicates the states for the bits > RGMII_TX_CLK_DELAY and RGMII_RX_CLK_DELAY as follows: > > RGMII Transmit/Receive Clock Delay > 0x0 = RGMII transmit clock is shifted with respect to transmit/receive data. > 0x1 = RGMII transmit clock is aligned with respect to transmit/receive data. > > This commit fixes the inversed behavior of these bits > > Fixes: 736b25afe284 ("net: dp83869: Add RGMII internal delay configuration") > > Signed-off-by: Daniel Gorsulowski <daniel.gorsulowski@esd.eu> Please no empty lines between "Fixes:" and other tags like "Signed-off-by:", all of the tags should be grouped together without any intervening empty lines. > - val &= ~(DP83869_RGMII_TX_CLK_DELAY_EN | > + val |= (DP83869_RGMII_TX_CLK_DELAY_EN | > DP83869_RGMII_RX_CLK_DELAY_EN); Please fix up the indentation of this last line here such that the first character is at the same column as the one after the openning parenthesis of the previous line.
On Tue, Aug 25, 2020 at 02:07:21PM +0200, Daniel Gorsulowski wrote: > The RGMII control register at 0x32 indicates the states for the bits > RGMII_TX_CLK_DELAY and RGMII_RX_CLK_DELAY as follows: > > RGMII Transmit/Receive Clock Delay > 0x0 = RGMII transmit clock is shifted with respect to transmit/receive data. > 0x1 = RGMII transmit clock is aligned with respect to transmit/receive data. > > This commit fixes the inversed behavior of these bits > > Fixes: 736b25afe284 ("net: dp83869: Add RGMII internal delay configuration") I Daniel I would like to see some sort of response from Dan Murphy about this. Andrew
Andrew On 8/25/20 8:37 AM, Andrew Lunn wrote: > On Tue, Aug 25, 2020 at 02:07:21PM +0200, Daniel Gorsulowski wrote: >> The RGMII control register at 0x32 indicates the states for the bits >> RGMII_TX_CLK_DELAY and RGMII_RX_CLK_DELAY as follows: >> >> RGMII Transmit/Receive Clock Delay >> 0x0 = RGMII transmit clock is shifted with respect to transmit/receive data. >> 0x1 = RGMII transmit clock is aligned with respect to transmit/receive data. >> >> This commit fixes the inversed behavior of these bits >> >> Fixes: 736b25afe284 ("net: dp83869: Add RGMII internal delay configuration") > I Daniel > > I would like to see some sort of response from Dan Murphy about this. Daniel had sent this privately to me and I encouraged him to send it in for review. Unfortunately he did not cc me on the patch he sent to the list. But reviewing it off the list it looks fine to me Dan
On Tue, Aug 25, 2020 at 02:57:35PM -0500, Dan Murphy wrote: > Andrew > > On 8/25/20 8:37 AM, Andrew Lunn wrote: > > On Tue, Aug 25, 2020 at 02:07:21PM +0200, Daniel Gorsulowski wrote: > > > The RGMII control register at 0x32 indicates the states for the bits > > > RGMII_TX_CLK_DELAY and RGMII_RX_CLK_DELAY as follows: > > > > > > RGMII Transmit/Receive Clock Delay > > > 0x0 = RGMII transmit clock is shifted with respect to transmit/receive data. > > > 0x1 = RGMII transmit clock is aligned with respect to transmit/receive data. > > > > > > This commit fixes the inversed behavior of these bits > > > > > > Fixes: 736b25afe284 ("net: dp83869: Add RGMII internal delay configuration") > > I Daniel > > > > I would like to see some sort of response from Dan Murphy about this. > > Daniel had sent this privately to me and I encouraged him to send it in for > review. > > Unfortunately he did not cc me on the patch he sent to the list. You should be able to reply to this email with a Reviewed-by: and patchwork will do the right thing. Andrew
Andrew On 8/26/20 7:58 AM, Andrew Lunn wrote: > On Tue, Aug 25, 2020 at 02:57:35PM -0500, Dan Murphy wrote: >> Andrew >> >> On 8/25/20 8:37 AM, Andrew Lunn wrote: >>> On Tue, Aug 25, 2020 at 02:07:21PM +0200, Daniel Gorsulowski wrote: >>>> The RGMII control register at 0x32 indicates the states for the bits >>>> RGMII_TX_CLK_DELAY and RGMII_RX_CLK_DELAY as follows: >>>> >>>> RGMII Transmit/Receive Clock Delay >>>> 0x0 = RGMII transmit clock is shifted with respect to transmit/receive data. >>>> 0x1 = RGMII transmit clock is aligned with respect to transmit/receive data. >>>> >>>> This commit fixes the inversed behavior of these bits >>>> >>>> Fixes: 736b25afe284 ("net: dp83869: Add RGMII internal delay configuration") >>> I Daniel >>> >>> I would like to see some sort of response from Dan Murphy about this. >> Daniel had sent this privately to me and I encouraged him to send it in for >> review. >> >> Unfortunately he did not cc me on the patch he sent to the list. > You should be able to reply to this email with a Reviewed-by: and > patchwork will do the right thing. Yep. I gave my ack on v2 of the patch set Dan > > Andrew
diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c index 58103152c601..3ad48673f865 100644 --- a/drivers/net/phy/dp83869.c +++ b/drivers/net/phy/dp83869.c @@ -427,18 +427,18 @@ static int dp83869_config_init(struct phy_device *phydev) return ret; val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL); - val &= ~(DP83869_RGMII_TX_CLK_DELAY_EN | + val |= (DP83869_RGMII_TX_CLK_DELAY_EN | DP83869_RGMII_RX_CLK_DELAY_EN); if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) - val |= (DP83869_RGMII_TX_CLK_DELAY_EN | + val &= ~(DP83869_RGMII_TX_CLK_DELAY_EN | DP83869_RGMII_RX_CLK_DELAY_EN); if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) - val |= DP83869_RGMII_TX_CLK_DELAY_EN; + val &= ~DP83869_RGMII_TX_CLK_DELAY_EN; if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) - val |= DP83869_RGMII_RX_CLK_DELAY_EN; + val &= ~DP83869_RGMII_RX_CLK_DELAY_EN; ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL, val);
The RGMII control register at 0x32 indicates the states for the bits RGMII_TX_CLK_DELAY and RGMII_RX_CLK_DELAY as follows: RGMII Transmit/Receive Clock Delay 0x0 = RGMII transmit clock is shifted with respect to transmit/receive data. 0x1 = RGMII transmit clock is aligned with respect to transmit/receive data. This commit fixes the inversed behavior of these bits Fixes: 736b25afe284 ("net: dp83869: Add RGMII internal delay configuration") Signed-off-by: Daniel Gorsulowski <daniel.gorsulowski@esd.eu> --- drivers/net/phy/dp83869.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)