diff mbox series

[net-next,2/8] igc: Add Receive Descriptor Minimum Threshold Count

Message ID 20200722213150.383393-3-anthony.l.nguyen@intel.com
State Changes Requested
Delegated to: David Miller
Headers show
Series 1GbE Intel Wired LAN Driver Updates 2020-07-22 | expand

Commit Message

Tony Nguyen July 22, 2020, 9:31 p.m. UTC 
From: Sasha Neftin <sasha.neftin@intel.com>

This register counts the number of events where the number of
descriptors in one of the Rx queues was lower than the threshold
defined for this queue.

Signed-off-by: Sasha Neftin <sasha.neftin@intel.com>
Tested-by: Aaron Brown <aaron.f.brown@intel.com>
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
---
 drivers/net/ethernet/intel/igc/igc_mac.c | 1 +
 1 file changed, 1 insertion(+)

Comments

Jakub Kicinski July 22, 2020, 10:49 p.m. UTC | #1 
On Wed, 22 Jul 2020 14:31:44 -0700 Tony Nguyen wrote:
> From: Sasha Neftin <sasha.neftin@intel.com>
> 
> This register counts the number of events where the number of
> descriptors in one of the Rx queues was lower than the threshold
> defined for this queue.

Cool, why do you need to read / clear it, though?
diff mbox series

Patch

diff --git a/drivers/net/ethernet/intel/igc/igc_mac.c b/drivers/net/ethernet/intel/igc/igc_mac.c
index 2d9ca3e1bdde..3a618e69514e 100644
--- a/drivers/net/ethernet/intel/igc/igc_mac.c
+++ b/drivers/net/ethernet/intel/igc/igc_mac.c
@@ -308,6 +308,7 @@  void igc_clear_hw_cntrs_base(struct igc_hw *hw)
 	rd32(IGC_TLPIC);
 	rd32(IGC_RLPIC);
 	rd32(IGC_HGPTC);
+	rd32(IGC_RXDMTC);
 	rd32(IGC_HGORCL);
 	rd32(IGC_HGORCH);
 	rd32(IGC_HGOTCL);