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[1/2] ag71xx: Add support for RMII, RGMII and SGMII

Message ID 20200302001830.14278-1-hauke@hauke-m.de
State Changes Requested
Delegated to: David Miller
Headers show
Series [1/2] ag71xx: Add support for RMII, RGMII and SGMII | expand

Commit Message

Hauke Mehrtens March 2, 2020, 12:18 a.m. UTC
The GMAC0 on the AR9344 also supports RMII and RGMII. This is an
external interface which gets connected to an external PHY or an
external switch. Without this patch the driver does not load on PHYs
configured to RMII or RGMII.

The QCA9563 often uses SGMII to connect to external switches.

This still misses the external interface configuration, but that was
also not done before the switch to phylink.

Fixes: 892e09153fa3 ("net: ag71xx: port to phylink")
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
---
 drivers/net/ethernet/atheros/ag71xx.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

Comments

Oleksij Rempel March 2, 2020, 11:01 a.m. UTC | #1
Am 02.03.20 um 01:18 schrieb Hauke Mehrtens:
> The GMAC0 on the AR9344 also supports RMII and RGMII. This is an
> external interface which gets connected to an external PHY or an
> external switch. Without this patch the driver does not load on PHYs
> configured to RMII or RGMII.
>
> The QCA9563 often uses SGMII to connect to external switches.
>
> This still misses the external interface configuration, but that was
> also not done before the switch to phylink.
>
> Fixes: 892e09153fa3 ("net: ag71xx: port to phylink")
> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
> ---
>  drivers/net/ethernet/atheros/ag71xx.c | 9 +++++++--
>  1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/net/ethernet/atheros/ag71xx.c b/drivers/net/ethernet/atheros/ag71xx.c
> index 02b7705393ca..69125f870363 100644
> --- a/drivers/net/ethernet/atheros/ag71xx.c
> +++ b/drivers/net/ethernet/atheros/ag71xx.c
> @@ -874,8 +874,11 @@ static void ag71xx_mac_validate(struct phylink_config *config,
>  	__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
>
>  	if (state->interface != PHY_INTERFACE_MODE_NA &&
> +	    state->interface != PHY_INTERFACE_MODE_MII &&
> +	    state->interface != PHY_INTERFACE_MODE_RMII &&
>  	    state->interface != PHY_INTERFACE_MODE_GMII &&
> -	    state->interface != PHY_INTERFACE_MODE_MII) {
> +	    state->interface != PHY_INTERFACE_MODE_SGMII &&
> +	    phy_interface_mode_is_rgmii(state->interface)) {
>  		bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
>  		return;
>  	}

Starting from now we need to do validation based on port and SoC. Not all mode are valid for all SoC
and ports. See ar9331_sw_phylink_validate as example.

> @@ -889,7 +892,9 @@ static void ag71xx_mac_validate(struct phylink_config *config,
>  	phylink_set(mask, 100baseT_Full);
>
>  	if (state->interface == PHY_INTERFACE_MODE_NA ||
> -	    state->interface == PHY_INTERFACE_MODE_GMII) {
> +	    state->interface == PHY_INTERFACE_MODE_GMII ||
> +	    state->interface == PHY_INTERFACE_MODE_SGMII ||
> +	    phy_interface_mode_is_rgmii(state->interface)) {
>  		phylink_set(mask, 1000baseT_Full);
>  		phylink_set(mask, 1000baseX_Full);
>  	}
>


--
Regards,
Oleksij
diff mbox series

Patch

diff --git a/drivers/net/ethernet/atheros/ag71xx.c b/drivers/net/ethernet/atheros/ag71xx.c
index 02b7705393ca..69125f870363 100644
--- a/drivers/net/ethernet/atheros/ag71xx.c
+++ b/drivers/net/ethernet/atheros/ag71xx.c
@@ -874,8 +874,11 @@  static void ag71xx_mac_validate(struct phylink_config *config,
 	__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
 
 	if (state->interface != PHY_INTERFACE_MODE_NA &&
+	    state->interface != PHY_INTERFACE_MODE_MII &&
+	    state->interface != PHY_INTERFACE_MODE_RMII &&
 	    state->interface != PHY_INTERFACE_MODE_GMII &&
-	    state->interface != PHY_INTERFACE_MODE_MII) {
+	    state->interface != PHY_INTERFACE_MODE_SGMII &&
+	    phy_interface_mode_is_rgmii(state->interface)) {
 		bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
 		return;
 	}
@@ -889,7 +892,9 @@  static void ag71xx_mac_validate(struct phylink_config *config,
 	phylink_set(mask, 100baseT_Full);
 
 	if (state->interface == PHY_INTERFACE_MODE_NA ||
-	    state->interface == PHY_INTERFACE_MODE_GMII) {
+	    state->interface == PHY_INTERFACE_MODE_GMII ||
+	    state->interface == PHY_INTERFACE_MODE_SGMII ||
+	    phy_interface_mode_is_rgmii(state->interface)) {
 		phylink_set(mask, 1000baseT_Full);
 		phylink_set(mask, 1000baseX_Full);
 	}