[V2] net: dsa: microchip: Always set regmap stride to 1

The regmap stride is set to 1 for regmap describing 8bit registers already.
However, for 16/32/64bit registers, the stride is 2/4/8 respectively. This
is not correct, as the switch protocol supports unaligned register reads
and writes and the KSZ87xx even uses such unaligned register accesses to
read e.g. MIB counter.

This patch fixes MIB counter access on KSZ87xx.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: David S. Miller <davem@davemloft.net>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: George McCollister <george.mccollister@gmail.com>
Cc: Tristram Ha <Tristram.Ha@microchip.com>
Cc: Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Cc: Woojung Huh <woojung.huh@microchip.com>
Fixes: 46558d601cb6 ("net: dsa: microchip: Initial SPI regmap support")
Fixes: 255b59ad0db2 ("net: dsa: microchip: Factor out regmap config generation into common header")
---
V2: Add Fixes: tags
---
 drivers/net/dsa/microchip/ksz_common.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

On Wed, Sep 25, 2019 at 5:08 PM Marek Vasut <marex@denx.de> wrote:
>
> The regmap stride is set to 1 for regmap describing 8bit registers already.
> However, for 16/32/64bit registers, the stride is 2/4/8 respectively. This
> is not correct, as the switch protocol supports unaligned register reads
> and writes and the KSZ87xx even uses such unaligned register accesses to
> read e.g. MIB counter.
>
> This patch fixes MIB counter access on KSZ87xx.

After looking through a couple hundred pages of register documentation
for KSZ9477 and KSZ9567 I find only registers that are aligned to
their width. In my testing the KSZ9567 works fine with and without the
patch. The only downside is that all of the unaligned registers
needlessly show up in the debugfs regmap, this doesn't really matter
though. As long as it fixes the issues on KSZ87xx this looks fine to
me.

>
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Andrew Lunn <andrew@lunn.ch>
> Cc: David S. Miller <davem@davemloft.net>
> Cc: Florian Fainelli <f.fainelli@gmail.com>
> Cc: George McCollister <george.mccollister@gmail.com>
> Cc: Tristram Ha <Tristram.Ha@microchip.com>
> Cc: Vivien Didelot <vivien.didelot@savoirfairelinux.com>
> Cc: Woojung Huh <woojung.huh@microchip.com>
> Fixes: 46558d601cb6 ("net: dsa: microchip: Initial SPI regmap support")
> Fixes: 255b59ad0db2 ("net: dsa: microchip: Factor out regmap config generation into common header")
> ---
> V2: Add Fixes: tags
> ---
>  drivers/net/dsa/microchip/ksz_common.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/net/dsa/microchip/ksz_common.h b/drivers/net/dsa/microchip/ksz_common.h
> index a24d8e61fbe7..dd60d0837fc6 100644
> --- a/drivers/net/dsa/microchip/ksz_common.h
> +++ b/drivers/net/dsa/microchip/ksz_common.h
> @@ -303,7 +303,7 @@ static inline void ksz_pwrite32(struct ksz_device *dev, int port, int offset,
>         {                                                               \
>                 .name = #width,                                         \
>                 .val_bits = (width),                                    \
> -               .reg_stride = (width) / 8,                              \
> +               .reg_stride = 1,                                        \
>                 .reg_bits = (regbits) + (regalign),                     \
>                 .pad_bits = (regpad),                                   \
>                 .max_register = BIT(regbits) - 1,                       \
> --
> 2.23.0
>

Reviewed-by: George McCollister <george.mccollister@gmail.com>

I tested the patch on the KSZ9567, not anything else FWIW:
Tested-by: George McCollister <george.mccollister@gmail.com>

From: Marek Vasut <marex@denx.de>
Date: Thu, 26 Sep 2019 00:08:42 +0200

> The regmap stride is set to 1 for regmap describing 8bit registers already.
> However, for 16/32/64bit registers, the stride is 2/4/8 respectively. This
> is not correct, as the switch protocol supports unaligned register reads
> and writes and the KSZ87xx even uses such unaligned register accesses to
> read e.g. MIB counter.
> 
> This patch fixes MIB counter access on KSZ87xx.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> Fixes: 46558d601cb6 ("net: dsa: microchip: Initial SPI regmap support")
> Fixes: 255b59ad0db2 ("net: dsa: microchip: Factor out regmap config generation into common header")

Applied.

On 9/26/19 3:52 PM, George McCollister wrote:
> On Wed, Sep 25, 2019 at 5:08 PM Marek Vasut wrote:
>>
>> The regmap stride is set to 1 for regmap describing 8bit registers already.
>> However, for 16/32/64bit registers, the stride is 2/4/8 respectively. This
>> is not correct, as the switch protocol supports unaligned register reads
>> and writes and the KSZ87xx even uses such unaligned register accesses to
>> read e.g. MIB counter.
>>
>> This patch fixes MIB counter access on KSZ87xx.
> 
> After looking through a couple hundred pages of register documentation
> for KSZ9477 and KSZ9567 I find only registers that are aligned to
> their width. In my testing the KSZ9567 works fine with and without the
> patch. The only downside is that all of the unaligned registers
> needlessly show up in the debugfs regmap, this doesn't really matter
> though. As long as it fixes the issues on KSZ87xx this looks fine to
> me.

Right.

To avoid exposing all registers through regmap debugfs entries, we would
have to define the regmap constrains for
readable/writeable/volatile/precious registers, which we should
eventually do anyway, but that's way beyond the scope of this fix.