From patchwork Sun Mar 24 03:23:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Oltean X-Patchwork-Id: 1062816 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="DuHngjFF"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44RjT40PH5z9sST for ; Sun, 24 Mar 2019 14:25:28 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728277AbfCXDZ0 (ORCPT ); Sat, 23 Mar 2019 23:25:26 -0400 Received: from mail-wr1-f65.google.com ([209.85.221.65]:44203 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728235AbfCXDZX (ORCPT ); Sat, 23 Mar 2019 23:25:23 -0400 Received: by mail-wr1-f65.google.com with SMTP id y7so2265421wrn.11 for ; Sat, 23 Mar 2019 20:25:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=cLoYr+ZDCSsSsSjog8W8KYYrQh13pQEN38XE9zZv7S0=; b=DuHngjFFAzkjYznbJduexgonrmExNcIox1RTgAdwd59vQtQ0ETw13mMoBogJOIXLEK nn4/jKiArT6PkROot93+FTZkE0puMekmnsemM8Ndh4mlQC5yyLuy93tOxkEZEIHLVaYs PlAz7aH3HYI3upqL9ppheXfiZ2IbBWKd8JtGiqILtyCV3em5um6tV7jv6r5zp3sSKYD2 BgAMsKtMO7DouhGXV0czRiw8E0dsR84kPzATazmQDSIohD7iNi7/FuRjFvAyHG2vpXJs kquXN6cHkvKFC7SRsYeuHv7CcN3fEFBg7lnX13elkfS/vuLV2SHyBxQ1kS3vyPzp72Fs +yiA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=cLoYr+ZDCSsSsSjog8W8KYYrQh13pQEN38XE9zZv7S0=; b=f176io/hhrEdBx1ElCNmdoL0pFxEfM9YsKVs3Qf2w9STwFT+UuieHjSR3ycJXREJSE Xn+f/ZqypR0TpcRifGcRjQIR+pItG4yAY0mAHw2uuBXT4BCXyk/UIDL2Ycr+44EeJ0GK HPaqVLLASH69eFA0swfCPGTupQCSc3rA1dbr2EuMD0YqAIQUPvR7yF2EN4K6ISNoOYdI oDZquPP4xk5krcaZzTrAlrTl9kz9PQFX4vOw/x4VeMbjAX82K4yhXhJSpBmlBAPfMTuG PxNQq7zNjP3gC2u437a6m2eq8SK7XnifU6o2l3S0IWhfVKei+D3/V0qkoIkxjTVplRa8 hrkQ== X-Gm-Message-State: APjAAAV2Fn4m6Hw21S4j+EFVSHC9dL+N75/IfST7KRbAOjq7MCC/LCLb UJeIb40lk145PFgbJOvHZFc= X-Google-Smtp-Source: APXvYqwcYY0/aamVpc9zIvg+BCUdoKw7XAVUmmfHylK0u5fsIwGp5vSFx1Vu5rhKL3AW0/hMTn0E4w== X-Received: by 2002:adf:cd90:: with SMTP id q16mr11012369wrj.75.1553397921817; Sat, 23 Mar 2019 20:25:21 -0700 (PDT) Received: from localhost.localdomain ([188.26.228.227]) by smtp.gmail.com with ESMTPSA id c20sm12243049wre.28.2019.03.23.20.25.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 23 Mar 2019 20:25:21 -0700 (PDT) From: Vladimir Oltean To: davem@davemloft.net, netdev@vger.kernel.org Cc: f.fainelli@gmail.com, andrew@lunn.ch, vivien.didelot@gmail.com, linus.walleij@linaro.org, Vladimir Oltean Subject: [RFC PATCH net-next 13/13] dt-bindings: net: dsa: Add documentation for NXP SJA1105 driver Date: Sun, 24 Mar 2019 05:23:46 +0200 Message-Id: <20190324032346.32394-14-olteanv@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190324032346.32394-1-olteanv@gmail.com> References: <20190324032346.32394-1-olteanv@gmail.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Signed-off-by: Vladimir Oltean Reviewed-by: Florian Fainelli --- .../devicetree/bindings/net/dsa/sja1105.txt | 123 ++++++++++++++++++ 1 file changed, 123 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/dsa/sja1105.txt diff --git a/Documentation/devicetree/bindings/net/dsa/sja1105.txt b/Documentation/devicetree/bindings/net/dsa/sja1105.txt new file mode 100644 index 000000000000..2c82b6fc37e3 --- /dev/null +++ b/Documentation/devicetree/bindings/net/dsa/sja1105.txt @@ -0,0 +1,123 @@ +NXP SJA1105 switch driver +========================= + +Required properties: + +- compatible: Must be "nxp,sja1105". Device ID identification (one of + E/T/P/Q/R/S) is performed by driver at probe time. Swapping pin-compatible + parts is possible with no DTS change. + +Optional properties: + +- sja1105,mac-mode, sja1105,phy-mode: Boolean properties that can be assigned + under each port node that is MII or RMII (has no effect for RGMII). By + default (unless otherwise specified) a port is configured as MAC if it is + driving a PHY (phy-handle is present) or as PHY if it is PHY-less (fixed-link + specified, presumably because it is connected to a MAC). These properties + are required in the case where SJA1105 ports are at both ends of an MII/RMII + PHY-less setup. One end would need to have sja1105,mac-mode, while the other + sja1105,phy-mode. + +See Documentation/devicetree/bindings/net/dsa/dsa.txt for the list of standard +DSA required and optional properties. + +Other observations: + +The SJA1105 SPI interface requires a CS-to-CLK time (t2 in UM10944) of at least +one half of t_CLK. At an SPI frequency of 1MHz, this means a minimum +cs_sck_delay of 500ns. Ensuring that this SPI timing requirement is observed +depends on the SPI bus master driver. + +Example: + +Ethernet switch connected via SPI to the host, CPU port wired to eth0: + +arch/arm/boot/dts/ls1021a-tsn.dts: + +/* SPI controller of the LS1021 */ +&dspi0 { + sja1105@1 { + reg = <0x1>; + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,sja1105"; + spi-max-frequency = <4000000>; + fsl,spi-cs-sck-delay = <1000>; + fsl,spi-sck-cs-delay = <1000>; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + /* ETH5 written on chassis */ + label = "swp5"; + phy-handle = <&rgmii_phy6>; + phy-mode = "rgmii"; + reg = <0>; + /* Implicit "sja1105,mac-mode;" */ + }; + port@1 { + /* ETH2 written on chassis */ + label = "swp2"; + phy-handle = <&rgmii_phy3>; + phy-mode = "rgmii"; + reg = <1>; + /* Implicit "sja1105,mac-mode;" */ + }; + port@2 { + /* ETH3 written on chassis */ + label = "swp3"; + phy-handle = <&rgmii_phy4>; + phy-mode = "rgmii"; + reg = <2>; + /* Implicit "sja1105,mac-mode;" */ + }; + port@3 { + /* ETH4 written on chassis */ + phy-handle = <&rgmii_phy5>; + label = "swp4"; + phy-mode = "rgmii"; + reg = <3>; + /* Implicit "sja1105,mac-mode;" */ + }; + port@4 { + /* Internal port connected to eth2 */ + ethernet = <&enet2>; + phy-mode = "rgmii"; + reg = <4>; + /* Implicit "sja1105,phy-mode;" */ + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; +}; + +/* MDIO controller of the LS1021 */ +&mdio0 { + /* BCM5464 */ + rgmii_phy3: ethernet-phy@3 { + reg = <0x3>; + }; + rgmii_phy4: ethernet-phy@4 { + reg = <0x4>; + }; + rgmii_phy5: ethernet-phy@5 { + reg = <0x5>; + }; + rgmii_phy6: ethernet-phy@6 { + reg = <0x6>; + }; +}; + +/* Ethernet master port of the LS1021 */ +&enet2 { + phy-connection-type = "rgmii"; + status = "ok"; + fixed-link { + speed = <1000>; + full-duplex; + }; +}; +