From patchwork Thu Feb 21 09:51:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Chevallier X-Patchwork-Id: 1045961 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=bootlin.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 444qWc5dtVz9sCH for ; Thu, 21 Feb 2019 20:52:12 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727747AbfBUJvv (ORCPT ); Thu, 21 Feb 2019 04:51:51 -0500 Received: from relay6-d.mail.gandi.net ([217.70.183.198]:42951 "EHLO relay6-d.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727682AbfBUJvu (ORCPT ); Thu, 21 Feb 2019 04:51:50 -0500 X-Originating-IP: 90.88.23.190 Received: from mc-bl-xps13.lan (aaubervilliers-681-1-81-190.w90-88.abo.wanadoo.fr [90.88.23.190]) (Authenticated sender: maxime.chevallier@bootlin.com) by relay6-d.mail.gandi.net (Postfix) with ESMTPSA id A5707C0017; Thu, 21 Feb 2019 09:51:45 +0000 (UTC) From: Maxime Chevallier To: davem@davemloft.net Cc: Maxime Chevallier , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Andrew Lunn , Florian Fainelli , Heiner Kallweit , Russell King , linux-arm-kernel@lists.infradead.org, Antoine Tenart , thomas.petazzoni@bootlin.com, gregory.clement@bootlin.com, miquel.raynal@bootlin.com, nadavh@marvell.com, stefanc@marvell.com, mw@semihalf.com Subject: [PATCH net-next 5/7] net: phy: marvell10g: Force reading of 2.5/5G Date: Thu, 21 Feb 2019 10:51:26 +0100 Message-Id: <20190221095128.28188-6-maxime.chevallier@bootlin.com> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190221095128.28188-1-maxime.chevallier@bootlin.com> References: <20190221095128.28188-1-maxime.chevallier@bootlin.com> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org As per 802.3bz, if bit 14 of (1.11) "PMA Extended Abilities" indicates whether or not we should read register (1.21) "2.52/5G PMA Extended Abilities", which contains information on the support of 2.5GBASET and 5GBASET. After testing on several variants of PHYS of this family, it appears that bit 14 in (1.11) isn't always set when it should be. PHYs 88X3310 (on MacchiatoBin) and 88E2010 do support 2.5G and 5GBASET, but don't have 1.11.14 set. Their register 1.21 is filled with the correct values, indicating 2.5G and 5G support. PHYs 88E2110 do have their 1.11.14 bit set, as it should. Signed-off-by: Maxime Chevallier --- drivers/net/phy/marvell10g.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c index 9323bcf15dbd..c48669d50653 100644 --- a/drivers/net/phy/marvell10g.c +++ b/drivers/net/phy/marvell10g.c @@ -27,6 +27,9 @@ #include #include +#define MV_PHY_ALASKA_NBT_QUIRK_MASK 0xfffffffe +#define MV_PHY_ALASKA_NBT_QUIRK_REV (MARVELL_PHY_ID_88X3310 | 0xa) + enum { MV_PCS_BASE_T = 0x0000, MV_PCS_BASE_R = 0x1000, @@ -231,6 +234,23 @@ static int mv3310_resume(struct phy_device *phydev) return mv3310_hwmon_config(phydev, true); } +/* Some PHYs in the Alaska family such as the 88X3310 and the 88E2010 + * don't set bit 14 in PMA Extended Abilities (1.11), although they do + * support 2.5GBASET and 5GBASET. For these models, we can still read their + * 2.5G/5G extended abilities register (1.21). We detect these models based on + * the PMA device identifier, with a mask matching models known to have this + * issue + */ +static bool mv3310_has_pma_ngbaset_quirk(struct phy_device *phydev) +{ + if (!(phydev->c45_ids.devices_in_package & MDIO_DEVS_PMAPMD)) + return false; + + /* Only some revisions of the 88X3310 family PMA seem to be impacted */ + return (phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] & + MV_PHY_ALASKA_NBT_QUIRK_MASK) == MV_PHY_ALASKA_NBT_QUIRK_REV; +} + static int mv3310_config_init(struct phy_device *phydev) { /* Check that the PHY interface type is compatible */ @@ -261,6 +281,21 @@ static int mv3310_get_features(struct phy_device *phydev) if (ret) return ret; + if (mv3310_has_pma_ngbaset_quirk(phydev)) { + val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, + MDIO_PMA_NG_EXTABLE); + if (val < 0) + return val; + + linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, + phydev->supported, + val & MDIO_PMA_NG_EXTABLE_2_5GBT); + + linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, + phydev->supported, + val & MDIO_PMA_NG_EXTABLE_5GBT); + } + return 0; }