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[79.208.157.51]) by smtp.gmail.com with ESMTPSA id h10sm17719521wmf.44.2019.02.04.13.35.56 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 04 Feb 2019 13:35:56 -0800 (PST) Received: from chuck by debian64.daheim with local (Exim 4.92-RC5) (envelope-from ) id 1gqluF-0006my-Gf; Mon, 04 Feb 2019 22:35:55 +0100 From: Christian Lamparter To: netdev@vger.kernel.org Cc: Florian Fainelli , Vivien Didelot , Andrew Lunn Subject: [PATCH v1] net: dsa: qca8k: implement DT-based ports <-> phy translation Date: Mon, 4 Feb 2019 22:35:55 +0100 Message-Id: <20190204213555.26054-1-chunkeey@gmail.com> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The QCA8337 enumerates 5 PHYs on the MDC/MDIO access: PHY0-PHY4. Based on the System Block Diagram in Section 1.2 of the QCA8337's datasheet. These PHYs are internally connected to MACs of PORT 1 - PORT 5. However, neither qca8k's slave mdio access functions qca8k_phy_read()/qca8k_phy_write() nor the dsa framework is set up for that. This version of the patch uses the existing phy-handle properties of each specified DSA Port in the DT to map each PORT/MAC to its exposed PHY on the MDIO bus. This is supported by the current binding document qca8k.txt as well. Signed-off-by: Christian Lamparter Signed-off-by: Christian Lamparter --- drivers/net/dsa/qca8k.c | 35 +++++++++++++++++++++++++++++++++-- 1 file changed, 33 insertions(+), 2 deletions(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index a4b6cda38016..6558b7ed855d 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -612,20 +613,50 @@ qca8k_adjust_link(struct dsa_switch *ds, int port, struct phy_device *phy) qca8k_port_set_status(priv, port, 1); } +static int +qca8k_to_real_phy(struct dsa_switch *ds, int phy) +{ + struct device_node *phy_dn, *port_dn; + int id; + + if (phy >= ds->num_ports) + return -EINVAL; + + port_dn = ds->ports[phy].dn; + if (!port_dn) + return -EINVAL; + + phy_dn = of_parse_phandle(port_dn, "phy-handle", 0); + if (!phy_dn) + return phy; + + id = of_mdio_parse_addr(ds->dev, phy_dn); + of_node_put(phy_dn); + return id; +} + static int qca8k_phy_read(struct dsa_switch *ds, int phy, int regnum) { struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; + int realphy = qca8k_to_real_phy(ds, phy); + + if (realphy < 0) + return realphy; - return mdiobus_read(priv->bus, phy, regnum); + return mdiobus_read(priv->bus, realphy, regnum); } static int qca8k_phy_write(struct dsa_switch *ds, int phy, int regnum, u16 val) { struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; + int realphy = qca8k_to_real_phy(ds, phy); + + if (realphy < 0) + return realphy; - return mdiobus_write(priv->bus, phy, regnum, val); + return mdiobus_write(priv->bus, realphy, regnum, val); } static void