@@ -542,13 +542,11 @@ struct pch_gbe_hw_stats {
/**
* struct pch_gbe_privdata - PCI Device ID driver data
* @phy_tx_clk_delay: Bool, configure the PHY TX delay in software
- * @phy_disable_hibernate: Bool, disable PHY hibernation
* @platform_init: Platform initialization callback, called from
* probe, prior to PHY initialization.
*/
struct pch_gbe_privdata {
bool phy_tx_clk_delay;
- bool phy_disable_hibernate;
int (*platform_init)(struct pci_dev *pdev);
};
@@ -2622,10 +2622,6 @@ static int pch_gbe_probe(struct pci_dev *pdev,
dev_dbg(&pdev->dev, "PCH Network Connection\n");
- /* Disable hibernation on certain platforms */
- if (adapter->pdata && adapter->pdata->phy_disable_hibernate)
- pch_gbe_phy_disable_hibernate(&adapter->hw);
-
device_set_wakeup_enable(&pdev->dev, 1);
return 0;
@@ -2663,7 +2659,6 @@ static int pch_gbe_minnow_platform_init(struct pci_dev *pdev)
static struct pch_gbe_privdata pch_gbe_minnow_privdata = {
.phy_tx_clk_delay = true,
- .phy_disable_hibernate = true,
.platform_init = pch_gbe_minnow_platform_init,
};
@@ -78,9 +78,7 @@
#define PHY_AR8031_DBG_OFF 0x1D
#define PHY_AR8031_DBG_DAT 0x1E
#define PHY_AR8031_SERDES 0x05
-#define PHY_AR8031_HIBERNATE 0x0B
#define PHY_AR8031_SERDES_TX_CLK_DLY 0x0100 /* TX clock delay of 2.0ns */
-#define PHY_AR8031_PS_HIB_EN 0x8000 /* Hibernate enable */
/* Phy Id Register (word 2) */
#define PHY_REVISION_MASK 0x000F
@@ -335,43 +333,3 @@ void pch_gbe_phy_init_setting(struct pch_gbe_hw *hw)
if (adapter->pdata && adapter->pdata->phy_tx_clk_delay)
pch_gbe_phy_tx_clk_delay(hw);
}
-
-/**
- * pch_gbe_phy_disable_hibernate - Disable the PHY low power state
- * @hw: Pointer to the HW structure
- * Returns
- * 0: Successful.
- * -EINVAL: Invalid argument.
- */
-int pch_gbe_phy_disable_hibernate(struct pch_gbe_hw *hw)
-{
- struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
- u16 mii_reg;
- int ret = 0;
-
- switch (hw->phy.id) {
- case PHY_AR803X_ID:
- netdev_dbg(adapter->netdev,
- "Disabling hibernation for AR803X PHY\n");
- ret = pch_gbe_phy_write_reg_miic(hw, PHY_AR8031_DBG_OFF,
- PHY_AR8031_HIBERNATE);
- if (ret)
- break;
-
- pch_gbe_phy_read_reg_miic(hw, PHY_AR8031_DBG_DAT, &mii_reg);
- mii_reg &= ~PHY_AR8031_PS_HIB_EN;
- ret = pch_gbe_phy_write_reg_miic(hw, PHY_AR8031_DBG_DAT,
- mii_reg);
- break;
- default:
- netdev_err(adapter->netdev,
- "Unknown PHY (%x), could not disable hibernation\n",
- hw->phy.id);
- return -EINVAL;
- }
-
- if (ret)
- netdev_err(adapter->netdev,
- "Could not disable PHY hibernation\n");
- return ret;
-}
@@ -30,6 +30,5 @@ void pch_gbe_phy_power_up(struct pch_gbe_hw *hw);
void pch_gbe_phy_power_down(struct pch_gbe_hw *hw);
void pch_gbe_phy_set_rgmii(struct pch_gbe_hw *hw);
void pch_gbe_phy_init_setting(struct pch_gbe_hw *hw);
-int pch_gbe_phy_disable_hibernate(struct pch_gbe_hw *hw);
#endif /* _PCH_GBE_PHY_H_ */
We should now be able to cope with the PHY entering hibernation, ie. ceasing to provide the RX clock, whilst the ethernet link is down. Remove the code responsible for disabling the AR8031 PHY's hibernation feature, allowing the PHY to enter its low power hibernation state. Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Andrew Lunn <andrew@lunn.ch> Cc: David S. Miller <davem@davemloft.net> Cc: netdev@vger.kernel.org --- Changes in v7: New patch .../net/ethernet/oki-semi/pch_gbe/pch_gbe.h | 2 - .../ethernet/oki-semi/pch_gbe/pch_gbe_main.c | 5 --- .../ethernet/oki-semi/pch_gbe/pch_gbe_phy.c | 42 ------------------- .../ethernet/oki-semi/pch_gbe/pch_gbe_phy.h | 1 - 4 files changed, 50 deletions(-)