From patchwork Sat Jun 23 03:17:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Burton X-Patchwork-Id: 933656 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=mips.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41CLHz1Xktz9s31 for ; Sat, 23 Jun 2018 13:18:55 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934787AbeFWDSx (ORCPT ); Fri, 22 Jun 2018 23:18:53 -0400 Received: from 9pmail.ess.barracuda.com ([64.235.150.224]:36572 "EHLO 9pmail.ess.barracuda.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934623AbeFWDSv (ORCPT ); Fri, 22 Jun 2018 23:18:51 -0400 Received: from mipsdag01.mipstec.com (mail1.mips.com [12.201.5.31]) by mx26.ess.sfj.cudaops.com (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=NO); Sat, 23 Jun 2018 03:18:46 +0000 Received: from mipsdag02.mipstec.com (10.20.40.47) by mipsdag01.mipstec.com (10.20.40.46) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1415.2; Fri, 22 Jun 2018 20:18:04 -0700 Received: from pburton-laptop.ba.imgtec.org (10.20.78.209) by mipsdag02.mipstec.com (10.20.40.47) with Microsoft SMTP Server id 15.1.1415.2 via Frontend Transport; Fri, 22 Jun 2018 20:18:04 -0700 From: Paul Burton To: CC: "David S . Miller" , Andrew Lunn , Paul Burton Subject: [PATCH 10/14] net: pch_gbe: Remove PCH_GBE_MAC_IFOP_RGMII define Date: Fri, 22 Jun 2018 20:17:49 -0700 Message-ID: <20180623031753.31893-11-paul.burton@mips.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180623031753.31893-1-paul.burton@mips.com> References: <20180623031753.31893-1-paul.burton@mips.com> MIME-Version: 1.0 X-BESS-ID: 1529723887-853316-12160-166002-10 X-BESS-VER: 2018.7-r1806151722 X-BESS-Apparent-Source-IP: 12.201.5.31 X-BESS-Envelope-From: Paul.Burton@mips.com X-BESS-Outbound-Spam-Score: 0.00 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.194356 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.00 using account:ESS59374 scores of KILL_LEVEL=7.0 tests=BSF_BESS_OUTBOUND X-BESS-Orig-Rcpt: netdev@vger.kernel.org,davem@davemloft.net,andrew@lunn.ch X-BESS-BRTS-Status: 1 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The pch_gbe driver currently presumes that the PHY is connected using RGMII, and would need further work to support other buses. It includes a define which is always set that conditionalises some of the RGMII-specific code regardless. Remove it. If we do ever support different MII buses then preprocessor defines won't be the best way to select between them anyway. Signed-off-by: Paul Burton --- drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c | 9 --------- drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_phy.h | 1 - 2 files changed, 10 deletions(-) diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c index 5846e8cf1750..11c42aa42b8a 100644 --- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c +++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c @@ -366,9 +366,7 @@ static void pch_gbe_mac_reset_hw(struct pch_gbe_hw *hw) /* Read the MAC address. and store to the private data */ pch_gbe_mac_read_mac_addr(hw); iowrite32(PCH_GBE_ALL_RST, &hw->reg->RESET); -#ifdef PCH_GBE_MAC_IFOP_RGMII iowrite32(PCH_GBE_MODE_GMII_ETHER, &hw->reg->MODE); -#endif pch_gbe_wait_clr_bit(&hw->reg->RESET, PCH_GBE_ALL_RST); /* Setup the receive addresses */ pch_gbe_mac_mar_set(hw, hw->mac.addr, 0); @@ -776,9 +774,7 @@ void pch_gbe_reset(struct pch_gbe_adapter *adapter) } pch_gbe_phy_init_setting(hw); /* Setup Mac interface option RGMII */ -#ifdef PCH_GBE_MAC_IFOP_RGMII pch_gbe_phy_set_rgmii(hw); -#endif } /** @@ -1044,7 +1040,6 @@ static void pch_gbe_set_rgmii_ctrl(struct pch_gbe_adapter *adapter, u16 speed, unsigned long rgmii = 0; /* Set the RGMII control. */ -#ifdef PCH_GBE_MAC_IFOP_RGMII switch (speed) { case SPEED_10: rgmii = (PCH_GBE_RGMII_RATE_2_5M | @@ -1060,10 +1055,6 @@ static void pch_gbe_set_rgmii_ctrl(struct pch_gbe_adapter *adapter, u16 speed, break; } iowrite32(rgmii, &hw->reg->RGMII_CTRL); -#else /* GMII */ - rgmii = 0; - iowrite32(rgmii, &hw->reg->RGMII_CTRL); -#endif } static void pch_gbe_set_mode(struct pch_gbe_adapter *adapter, u16 speed, u16 duplex) diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_phy.h b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_phy.h index efb955be8cac..23ac38711619 100644 --- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_phy.h +++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_phy.h @@ -21,7 +21,6 @@ #define PCH_GBE_PHY_REGS_LEN 32 #define PCH_GBE_PHY_RESET_DELAY_US 10 -#define PCH_GBE_MAC_IFOP_RGMII s32 pch_gbe_phy_get_id(struct pch_gbe_hw *hw); s32 pch_gbe_phy_read_reg_miic(struct pch_gbe_hw *hw, u32 offset, u16 *data);