From patchwork Thu May 10 23:16:57 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Burton X-Patchwork-Id: 911627 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=mips.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40hqWp6DGBz9s16 for ; Fri, 11 May 2018 09:42:14 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750989AbeEJXmM (ORCPT ); Thu, 10 May 2018 19:42:12 -0400 Received: from 9pmail.ess.barracuda.com ([64.235.150.225]:34310 "EHLO 9pmail.ess.barracuda.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751169AbeEJXmL (ORCPT ); Thu, 10 May 2018 19:42:11 -0400 Received: from mipsdag02.mipstec.com (mail2.mips.com [12.201.5.32]) by mx3.ess.sfj.cudaops.com (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=NO); Thu, 10 May 2018 23:39:53 +0000 Received: from mipsdag02.mipstec.com (10.20.40.47) by mipsdag02.mipstec.com (10.20.40.47) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1415.2; Thu, 10 May 2018 16:17:28 -0700 Received: from pburton-laptop.mipstec.com (10.20.1.18) by mipsdag02.mipstec.com (10.20.40.47) with Microsoft SMTP Server id 15.1.1415.2 via Frontend Transport; Thu, 10 May 2018 16:17:28 -0700 From: Paul Burton To: CC: , "David S . Miller" , Andrew Lunn , Paul Burton Subject: [PATCH v6 6/6] MIPS: Boston: Adjust DT for pch_gbe PHY support Date: Thu, 10 May 2018 16:16:57 -0700 Message-ID: <20180510231657.28503-7-paul.burton@mips.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180510231657.28503-1-paul.burton@mips.com> References: <20180510231657.28503-1-paul.burton@mips.com> MIME-Version: 1.0 X-BESS-ID: 1525995592-298554-6768-4804-2 X-BESS-VER: 2018.6-r1805011734 X-BESS-Apparent-Source-IP: 12.201.5.32 X-BESS-Outbound-Spam-Score: 0.00 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.192890 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.00 using account:ESS59374 scores of KILL_LEVEL=7.0 tests=BSF_BESS_OUTBOUND X-BESS-BRTS-Status: 1 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The pch_gbe driver support for PHY reset GPIOs is now provided by the standard phylib infrastructure, using a standard PHY binding. Adjust the Boston devicetree to make use of the standard PHY binding. This is possible because we bundle the DT along with the kernel binary into a Flattened Image Tree, so the DT and kernel are always shipped together for the Boston platform. Signed-off-by: Paul Burton Cc: Andrew Lunn Cc: David S. Miller Cc: linux-mips@linux-mips.org Cc: netdev@vger.kernel.org --- Changes in v6: - New patch. Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None arch/mips/boot/dts/img/boston.dts | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/arch/mips/boot/dts/img/boston.dts b/arch/mips/boot/dts/img/boston.dts index 65af3f6ba81c..cb55f7ba20c3 100644 --- a/arch/mips/boot/dts/img/boston.dts +++ b/arch/mips/boot/dts/img/boston.dts @@ -144,8 +144,17 @@ eg20t_mac@2,0,1 { compatible = "pci8086,8802"; reg = <0x00020100 0 0 0 0>; - phy-reset-gpios = <&eg20t_gpio 6 - GPIO_ACTIVE_LOW>; + + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy@0 { + compatible = "ethernet-phy-id001c.c915"; + reg = <0>; + reset-gpios = <&eg20t_gpio 6 GPIO_ACTIVE_LOW>; + reset-assert-us = <25000>; + reset-deassert-us = <25000>; + }; }; eg20t_gpio: eg20t_gpio@2,0,2 {