| Message ID | 20171215021014.231308-3-yixun.lan@amlogic.com |
|---|---|
| State | Not Applicable, archived |
| Delegated to: | David Miller |
| Headers | show |
| Series | Add ethernet support for Meson-AXG SoC | expand |
Yixun Lan <yixun.lan@amlogic.com> writes: > This is tested in the S400 dev board which use a RTL8211F PHY, > and the pins connect to the 'eth_rgmii_y_pins' group. > > Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> > Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> > --- > arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts > index 70eca1f8736a..b8c4f1913d28 100644 > --- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts > +++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts > @@ -20,3 +20,10 @@ > &uart_AO { > status = "okay"; > }; > + > +ðmac { > + status = "okay"; > + phy-mode = "rgmii"; > + pinctrl-0 = <ð_rgmii_y_pins>; > + pinctrl-names = "default"; > +}; Minor nit: we try to keep these sorted alphabetically. Can you move this above the uart_A0 one? Note: if PATCH 1/1 had applied cleanly, I would have fixed this up myself and not required a respin. Kevin
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts index 70eca1f8736a..b8c4f1913d28 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts +++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts @@ -20,3 +20,10 @@ &uart_AO { status = "okay"; }; + +ðmac { + status = "okay"; + phy-mode = "rgmii"; + pinctrl-0 = <ð_rgmii_y_pins>; + pinctrl-names = "default"; +};