From patchwork Mon Nov 13 19:02:27 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 837508 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3ybKlZ5582z9sBZ for ; Tue, 14 Nov 2017 06:02:50 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752637AbdKMTCj (ORCPT ); Mon, 13 Nov 2017 14:02:39 -0500 Received: from bastet.se.axis.com ([195.60.68.11]:54087 "EHLO bastet.se.axis.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752431AbdKMTCg (ORCPT ); Mon, 13 Nov 2017 14:02:36 -0500 Received: from localhost (localhost [127.0.0.1]) by bastet.se.axis.com (Postfix) with ESMTP id 5AF45183E6; Mon, 13 Nov 2017 20:02:35 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at bastet.se.axis.com Received: from bastet.se.axis.com ([IPv6:::ffff:127.0.0.1]) by localhost (bastet.se.axis.com [::ffff:127.0.0.1]) (amavisd-new, port 10024) with LMTP id hbSmhNieDCMT; Mon, 13 Nov 2017 20:02:33 +0100 (CET) Received: from boulder02.se.axis.com (boulder02.se.axis.com [10.0.8.16]) by bastet.se.axis.com (Postfix) with ESMTPS id DD23B183DA; Mon, 13 Nov 2017 20:02:33 +0100 (CET) Received: from boulder02.se.axis.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C1E3B1A05E; Mon, 13 Nov 2017 20:02:33 +0100 (CET) Received: from boulder02.se.axis.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B631B1A058; Mon, 13 Nov 2017 20:02:33 +0100 (CET) Received: from seth.se.axis.com (unknown [10.0.2.172]) by boulder02.se.axis.com (Postfix) with ESMTP; Mon, 13 Nov 2017 20:02:33 +0100 (CET) Received: from lnxartpec1.se.axis.com (lnxartpec1.se.axis.com [10.88.4.10]) by seth.se.axis.com (Postfix) with ESMTP id A9761B0; Mon, 13 Nov 2017 20:02:33 +0100 (CET) Received: by lnxartpec1.se.axis.com (Postfix, from userid 20283) id A4282400F9; Mon, 13 Nov 2017 20:02:33 +0100 (CET) From: Niklas Cassel To: Giuseppe Cavallaro , Alexandre Torgue Cc: Niklas Cassel , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next] net: stmmac: fix LPI transitioning for dwmac4 Date: Mon, 13 Nov 2017 20:02:27 +0100 Message-Id: <20171113190227.28407-1-niklas.cassel@axis.com> X-Mailer: git-send-email 2.14.2 X-TM-AS-GCONF: 00 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The LPI transitioning logic in stmmac_main uses priv->tx_path_in_lpi_mode to enter/exit LPI. However, priv->tx_path_in_lpi_mode is assigned using the return value from host_irq_status(). So for dwmac4, priv->tx_path_in_lpi_mode was always false, to stmmac_tx_clean() would always try to put us in eee mode, and stmmac_xmit() would never take us out of eee mode. To fix this, make host_irq_status() read and return the LPI irq status also for dwmac4. This also increments the existing LPI counters, so that ethtool --statistics shows LPI transitions also for dwmac4. For dwmac1000, irqs are enabled/disabled using the register is named "Interrupt Mask Register", and thus setting a bit disables that specific irq. For dwmac4 the matching register is named "MAC_Interrupt_Enable", and thus setting a bit enables that specific irq. Looking at dwmac1000_core.c, the irqs that are always enabled are: LPI and PMT. Looking at dwmac4_core.c, the irqs that are always enabled are: PMT. To be able to read the LPI irq status, we need to enable the LPI irq also for dwmac4. Signed-off-by: Niklas Cassel --- drivers/net/ethernet/stmicro/stmmac/dwmac4.h | 7 ++++++- drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c | 19 +++++++++++++++++++ 2 files changed, 25 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h index aeda3ab2d761..789dad8a07b5 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h @@ -98,7 +98,7 @@ #define GMAC_PCS_IRQ_DEFAULT (GMAC_INT_RGSMIIS | GMAC_INT_PCS_LINK | \ GMAC_INT_PCS_ANE) -#define GMAC_INT_DEFAULT_MASK GMAC_INT_PMT_EN +#define GMAC_INT_DEFAULT_MASK (GMAC_INT_PMT_EN | GMAC_INT_LPI_EN) enum dwmac4_irq_status { time_stamp_irq = 0x00001000, @@ -106,6 +106,7 @@ enum dwmac4_irq_status { mmc_tx_irq = 0x00000400, mmc_rx_irq = 0x00000200, mmc_irq = 0x00000100, + lpi_irq = 0x00000020, pmt_irq = 0x00000010, }; @@ -132,6 +133,10 @@ enum power_event { #define GMAC4_LPI_CTRL_STATUS_LPITXA BIT(19) /* Enable LPI TX Automate */ #define GMAC4_LPI_CTRL_STATUS_PLS BIT(17) /* PHY Link Status */ #define GMAC4_LPI_CTRL_STATUS_LPIEN BIT(16) /* LPI Enable */ +#define GMAC4_LPI_CTRL_STATUS_RLPIEX BIT(3) /* Receive LPI Exit */ +#define GMAC4_LPI_CTRL_STATUS_RLPIEN BIT(2) /* Receive LPI Entry */ +#define GMAC4_LPI_CTRL_STATUS_TLPIEX BIT(1) /* Transmit LPI Exit */ +#define GMAC4_LPI_CTRL_STATUS_TLPIEN BIT(0) /* Transmit LPI Entry */ /* MAC Debug bitmap */ #define GMAC_DEBUG_TFCSTS_MASK GENMASK(18, 17) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c index 2f7d7ec59962..f3ed8f7853eb 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c @@ -580,6 +580,25 @@ static int dwmac4_irq_status(struct mac_device_info *hw, x->irq_receive_pmt_irq_n++; } + /* MAC tx/rx EEE LPI entry/exit interrupts */ + if (intr_status & lpi_irq) { + /* Clear LPI interrupt by reading MAC_LPI_Control_Status */ + u32 status = readl(ioaddr + GMAC4_LPI_CTRL_STATUS); + + if (status & GMAC4_LPI_CTRL_STATUS_TLPIEN) { + ret |= CORE_IRQ_TX_PATH_IN_LPI_MODE; + x->irq_tx_path_in_lpi_mode_n++; + } + if (status & GMAC4_LPI_CTRL_STATUS_TLPIEX) { + ret |= CORE_IRQ_TX_PATH_EXIT_LPI_MODE; + x->irq_tx_path_exit_lpi_mode_n++; + } + if (status & GMAC4_LPI_CTRL_STATUS_RLPIEN) + x->irq_rx_path_in_lpi_mode_n++; + if (status & GMAC4_LPI_CTRL_STATUS_RLPIEX) + x->irq_rx_path_exit_lpi_mode_n++; + } + dwmac_pcs_isr(ioaddr, GMAC_PCS_BASE, intr_status, x); if (intr_status & PCS_RGSMIIIS_IRQ) dwmac4_phystatus(ioaddr, x);