From patchwork Mon Nov 13 08:01:55 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yixun Lan X-Patchwork-Id: 837387 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yb3RS3M30z9sNw for ; Mon, 13 Nov 2017 19:17:56 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752053AbdKMIRx (ORCPT ); Mon, 13 Nov 2017 03:17:53 -0500 Received: from mail-sh2.amlogic.com ([58.32.228.45]:34294 "EHLO mail-sh2.amlogic.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751718AbdKMIRx (ORCPT ); Mon, 13 Nov 2017 03:17:53 -0500 X-Greylist: delayed 904 seconds by postgrey-1.27 at vger.kernel.org; Mon, 13 Nov 2017 03:17:52 EST Received: from localhost.localdomain (10.18.20.164) by mail-sh2.amlogic.com (10.18.11.6) with Microsoft SMTP Server id 15.0.1320.4; Mon, 13 Nov 2017 16:02:14 +0800 From: Yixun Lan To: , Kevin Hilman CC: Neil Armstrong , Jerome Brunet , Giuseppe Cavallaro , Alexandre Torgue , Carlo Caione , Yixun Lan , , , , Subject: [PATCH] ARM64: dts: meson-axg: add ethernet mac controller Date: Mon, 13 Nov 2017 16:01:55 +0800 Message-ID: <20171113080155.2463-1-yixun.lan@amlogic.com> X-Mailer: git-send-email 2.14.1 MIME-Version: 1.0 X-Originating-IP: [10.18.20.164] Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Add DT info for the stmmac ethernet MAC which found in the Amlogic's Meson-AXG SoC, also describe the ethernet pinctrl & clock information here. This is tested in the S400 dev board which use a RTL8211F PHY, and the pins connect to the 'eth_rgmii_y_pins' group. Signed-off-by: Yixun Lan Reviewed-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 7 ++++ arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 53 ++++++++++++++++++++++++++ 2 files changed, 60 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts index 9eb6aaee155d..7b39a9fe2b0f 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts +++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts @@ -21,3 +21,10 @@ status = "okay"; }; +ðmac { + status = "okay"; + phy-mode = "rgmii"; + + pinctrl-0 = <ð_rgmii_y_pins>; + pinctrl-names = "default"; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index 65945c6c8b65..57faaa9d8013 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -157,6 +157,19 @@ #address-cells = <0>; }; + ethmac: ethernet@ff3f0000 { + compatible = "amlogic,meson-axg-dwmac", "amlogic,meson-gxbb-dwmac", "snps,dwmac"; + reg = <0x0 0xff3f0000 0x0 0x10000 + 0x0 0xff634540 0x0 0x8>; + interrupts = ; + interrupt-names = "macirq"; + status = "disabled"; + clocks = <&clkc CLKID_ETH>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_MPLL2>; + clock-names = "stmmaceth", "clkin0", "clkin1"; + }; + hiubus: hiubus@ff63c000 { compatible = "simple-bus"; reg = <0x0 0xff63c000 0x0 0x1c00>; @@ -203,6 +216,46 @@ #gpio-cells = <2>; gpio-ranges = <&pinctrl_periphs 0 0 86>; }; + + eth_rgmii_x_pins: eth-x-rgmii { + mux { + groups = "eth_mdio_x", + "eth_mdc_x", + "eth_rgmii_rx_clk_x", + "eth_rx_dv_x", + "eth_rxd0_x", + "eth_rxd1_x", + "eth_rxd2_rgmii", + "eth_rxd3_rgmii", + "eth_rgmii_tx_clk", + "eth_txen_x", + "eth_txd0_x", + "eth_txd1_x", + "eth_txd2_rgmii", + "eth_txd3_rgmii"; + function = "eth"; + }; + }; + + eth_rgmii_y_pins: eth-y-rgmii { + mux { + groups = "eth_mdio_y", + "eth_mdc_y", + "eth_rgmii_rx_clk_y", + "eth_rx_dv_y", + "eth_rxd0_y", + "eth_rxd1_y", + "eth_rxd2_rgmii", + "eth_rxd3_rgmii", + "eth_rgmii_tx_clk", + "eth_txen_y", + "eth_txd0_y", + "eth_txd1_y", + "eth_txd2_rgmii", + "eth_txd3_rgmii"; + function = "eth"; + }; + }; }; };