From patchwork Fri Sep 1 11:56:03 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 808666 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="IufRVJmy"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3xkHq21QKqz9s7M for ; Fri, 1 Sep 2017 21:59:42 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752052AbdIAL72 (ORCPT ); Fri, 1 Sep 2017 07:59:28 -0400 Received: from mail-wr0-f196.google.com ([209.85.128.196]:35248 "EHLO mail-wr0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751715AbdIAL6S (ORCPT ); Fri, 1 Sep 2017 07:58:18 -0400 Received: by mail-wr0-f196.google.com with SMTP id a47so3561wra.2; Fri, 01 Sep 2017 04:58:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=zdxlwoWwSQe6cJCSvJJ47Vobly+MygkCTskdI+WtCMk=; b=IufRVJmydXZPB7ZOgo2jGU82OFUeaJtf3p79dbORm196u/VApap7u/dkllbPJn/X/a vU5C1tjJArfe02cbBfVKgmObpEzaZage/TRfC1ySkM7kV46rx5C8HY81zlHcTto6I1Ve VrHhc7T6EvgtcRvxvsUxhJxSnWJmDpoQ45FfkYqLEQ0ZJhreRgdfdwxsJfs3FA3Bi1g5 PZYE+0lhFYGr67RSxYdcHY+e3xCgz/sEECDetnl2dzbHZI/SGISeMq30UtwnBwXSESo3 /jsaqodJupnoerd9wP/tJxqGOthiNnnnESAkhgknWGxzwVHr9ZZiJi65VNndfG9FcVhC 3rtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=zdxlwoWwSQe6cJCSvJJ47Vobly+MygkCTskdI+WtCMk=; b=OC2JPyhvy1hEZ1oIkchC7zL0Pyxdt5b3o/+iljCUgnPqijX1i1at2SeCgV1KHdFsAe bP8GlPjFcVWLFGHPQ8VYD3ducrQoevIQUgQYPIgNt+YRIxovRsXEPLFuRtkj1k+bQpqy KpgjlgLcfy3HBspnda3FdrrJwsePIs9I4cetRp1MqS4v7j1RuvbYnJyi9X0+dAqBOmiA nQiJCd6t0MOK9pOAKhth2GqhxAoEGVy+g2kgBVpD9OfyHVAjjqfT8jJMAZXc8Qnu4W/3 WjtciS0yxEXEBWyriPalut8tHyTGIRCYzgwkFa8LZwbq8wfqotvwa9mnY/Fffe+CI8N7 0ILw== X-Gm-Message-State: AHPjjUjgHiwbwX1pS0KHhE9FbLqTCDmrRr9FUF78sj6MHKQj3tEbPmeq BEP4LzRF9sQH6w== X-Google-Smtp-Source: ADKCNb4C9W07TLTBu9xUQ+H2cDcjG28YzqBeNEZz/lTOuM1qYWDuG20B9ryMwsZPIH0VZgOc7xoRoQ== X-Received: by 10.223.166.38 with SMTP id k35mr1003156wrc.183.1504267097003; Fri, 01 Sep 2017 04:58:17 -0700 (PDT) Received: from Red.local (LFbn1-1-65-78.w90-118.abo.wanadoo.fr. [90.118.156.78]) by smtp.googlemail.com with ESMTPSA id p80sm3292wmf.13.2017.09.01.04.58.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 01 Sep 2017 04:58:16 -0700 (PDT) From: Corentin Labbe To: andrew@lunn.ch, f.fainelli@gmail.com Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Corentin Labbe Subject: [PATCH v2 4/5] net: mdio-mux-mmioreg: Can handle 8/16/32 bits registers Date: Fri, 1 Sep 2017 13:56:03 +0200 Message-Id: <20170901115604.27513-5-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170901115604.27513-1-clabbe.montjoie@gmail.com> References: <20170901115604.27513-1-clabbe.montjoie@gmail.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org This patch fix an old information that mdio-mux-mmioreg can only handle 8bit registers. This is not true anymore. Signed-off-by: Corentin Labbe Reviewed-by: Andrew Lunn --- drivers/net/phy/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 5afe6fdcc968..a9d16a3af514 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -85,7 +85,7 @@ config MDIO_BUS_MUX_MMIOREG parent bus. Child bus selection is under the control of one of the FPGA's registers. - Currently, only 8-bit registers are supported. + Currently, only 8/16/32 bits registers are supported. config MDIO_CAVIUM tristate