From patchwork Tue Aug 22 18:11:40 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 804614 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="oSjhlYVO"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3xcJYg0k4pz9sDB for ; Wed, 23 Aug 2017 04:12:23 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752351AbdHVSLw (ORCPT ); Tue, 22 Aug 2017 14:11:52 -0400 Received: from mail-wm0-f66.google.com ([74.125.82.66]:35199 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752029AbdHVSLu (ORCPT ); Tue, 22 Aug 2017 14:11:50 -0400 Received: by mail-wm0-f66.google.com with SMTP id r77so9313894wmd.2; Tue, 22 Aug 2017 11:11:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=+8scy55slXx8/eh8qdkKsU7Ix8sBrmlkP4qSkMHK5r8=; b=oSjhlYVOLTVErgKCMBbhEmTuzfCfDVRxF4VfSmSp51zXqKfsb9JOFNPjqn/tcxIzTP OUBI3mW4wlF9oOyxQKfpZax32KMRSu+MAeKY+XzmIRDwPolLqTs93DvElWh1ttU7jl85 wmK8dnHVe/XqzZUSrU9FTuTTPo+GtcJEqZ+SU+qB5NiA4mDF0v/NHtUdmbTmxNHI2c/7 i5aWdV0g5NmKAywnCKSuXF0zq2JXcmw0jeiKNDnsA/bH9//xoYljxGF6M2WaPswqV1lg +TNhGbIfT7ia/JJiPpCCk0iHTe6xE4Z+lbFa1t2gudLwXGFeNeSWlI190nyUB0AooRi2 9jxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=+8scy55slXx8/eh8qdkKsU7Ix8sBrmlkP4qSkMHK5r8=; b=QVPZpG/G7Fu3HxDM4pUCWRo1quGUE0Ftpz+l6c/gvXA/9yNXnVYfC1n4qx/lbQGfW8 u0UES1dvOjd0OFiFjAQDY6PFA1sXAondDOuI4WCwW5IrG7YWl8pBGzPEGPzvf5mHcSgk DwxFsxUsfgK1g2CYP6hbPPut+An2n4Hs8r5ZCTFMO+cZblO+HQOZtNuvjhe1q7nWNZmh LrZ1q1y8ZOdTsDsiqlKWm5CHjuIGmrDAYDGYQH3BOU4Th6yIH5c8Gue26Ff0WrOpuGTg QE/u3K2yfU/NnJe17uUia0681VSORC8ODvMAA76dr58Qq6bLmqnk5RH3v3vh0wPOb4SK CrIQ== X-Gm-Message-State: AHYfb5j+IK/FfsW8QuDuAUEm2iYdbD4WL0DxiV1I8FYqblOfOprkt/vx mIOy6eNJCjgfiw== X-Received: by 10.28.157.81 with SMTP id g78mr247606wme.85.1503425508586; Tue, 22 Aug 2017 11:11:48 -0700 (PDT) Received: from Red ([2a01:cb1d:16e:1300:2e56:dcff:fed2:c6d6]) by smtp.googlemail.com with ESMTPSA id g133sm17244607wmd.48.2017.08.22.11.11.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 22 Aug 2017 11:11:47 -0700 (PDT) Date: Tue, 22 Aug 2017 20:11:40 +0200 From: Corentin Labbe To: Florian Fainelli Cc: Chen-Yu Tsai , Andrew Lunn , Maxime Ripard , Rob Herring , Mark Rutland , Russell King , Giuseppe Cavallaro , Alexandre Torgue , devicetree , linux-arm-kernel , linux-kernel , netdev Subject: Re: [PATCH v3 3/4] net: stmmac: register parent MDIO node for sun8i-h3-emac Message-ID: <20170822181140.GA11596@Red> References: <20170819185025.GB13266@Red> <20170819203836.GA21567@lunn.ch> <20170820065757.GA6081@Red> <20170820142545.GB24150@lunn.ch> <20170821132015.GB1703@lunn.ch> <20170821133104.qvrhvwin2rdg4aqo@flea.lan> <20170821142321.GE1703@lunn.ch> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.7.2 (2016-11-26) Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org On Tue, Aug 22, 2017 at 09:40:24AM -0700, Florian Fainelli wrote: > On 08/22/2017 08:39 AM, Chen-Yu Tsai wrote: > > On Mon, Aug 21, 2017 at 10:23 PM, Andrew Lunn wrote: > >>> All muxes are mostly always represented the same way afaik, or do you > >>> want to simply introduce a new compatible / property? > >> > >> + mdio-mux { > >> + compatible = "allwinner,sun8i-h3-mdio-switch"; > >> + mdio-parent-bus = <&mdio_parent>; > >> + #address-cells = <1>; > >> + #size-cells = <0>; > >> + > >> + internal_mdio: mdio@1 { > >> reg = <1>; > >> - clocks = <&ccu CLK_BUS_EPHY>; > >> - resets = <&ccu RST_BUS_EPHY>; > >> + #address-cells = <1>; > >> + #size-cells = <0>; > >> + int_mii_phy: ethernet-phy@1 { > >> + compatible = "ethernet-phy-ieee802.3-c22"; > >> + reg = <1>; > >> + clocks = <&ccu CLK_BUS_EPHY>; > >> + resets = <&ccu RST_BUS_EPHY>; > >> + phy-is-integrated; > >> + }; > >> + }; > >> + mdio: mdio@0 { > >> + reg = <0>; > >> + #address-cells = <1>; > >> + #size-cells = <0>; > >> }; > >> > >> Hi Maxim > >> > >> Anybody who knows the MDIO-mux code/binding, knows that it is a run > >> time mux. You swap the mux per MDIO transaction. You can access all > >> the PHY and switches on the mux'ed MDIO bus. > >> > >> However here, it is effectively a boot-time MUX. You cannot change it > >> on the fly. What happens when somebody has a phandle to a PHY on the > >> internal and a phandle to a phy on the external? Does the driver at > >> least return -EINVAL, or -EBUSY? Is there a representation which > >> eliminates this possibility? > > > > There is only one controller. Either you use the internal PHY, which > > is then directly coupled (no magnetics needed) to the RJ45 port, or > > you use an external PHY over MII/RMII/RGMII. You could supposedly > > have both on a board, and let the user choose one. But why bother > > with the extra complexity and cost? Either you use the internal PHY > > at 100M, or an external RGMII PHY for gigabit speeds. > > I agree, there is no point in over-engineering any of this. I don't > think there is actually any MDIO mux per-se in that the MDIO clock and > data lines are muxed, however there has to be some kind of built-in port > multiplexer that lets you chose between connecting to the internal PHY > and any external PHY/MAC, but that is not what a "mdio-mux" node represents. > > > > > So I think what you are saying is either impossible or engineering-wise > > a very stupid design, like using an external MAC with a discrete PHY > > connected to the internal MAC's MDIO bus, while using the internal MAC > > with the internal PHY. > > > > Now can we please decide on something? We're a week and a half from > > the 4.13 release. If mdio-mux is wrong, then we could have two mdio > > nodes (internal-mdio & external-mdio). > > I really don't see a need for a mdio-mux in the first place, just have > one MDIO controller (current state) sub-node which describes the > built-in STMMAC MDIO controller and declare the internal PHY as a child > node (along with 'phy-is-integrated'). If a different configuration is > used, then just put the external PHY as a child node there. > > If fixed-link is required, the mdio node becomes unused anyway. > > Works for everyone? If we put an external PHY with reg=1 as a child of internal MDIO, il will be merged with internal PHY node and get phy-is-integrated. Does two MDIO node "internal-mdio" and "mdio" works for you ? (We keep "mdio" for external MDIO for reducing the number of patchs) Thanks Regards diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 4b599b5d26f6..d5e7cf0d9454 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -417,7 +417,8 @@ #size-cells = <0>; status = "disabled"; - mdio: mdio { + /* Only one MDIO is usable at the time */ + internal_mdio: mdio@1 { #address-cells = <1>; #size-cells = <0>; int_mii_phy: ethernet-phy@1 { @@ -425,8 +426,13 @@ reg = <1>; clocks = <&ccu CLK_BUS_EPHY>; resets = <&ccu RST_BUS_EPHY>; + phy-is-integrated; }; }; + mdio: mdio@0 { + #address-cells = <1>; + #size-cells = <0>; + }; }; spi0: spi@01c68000 {