From patchwork Wed Jun 28 16:32:21 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Grzeschik X-Patchwork-Id: 781771 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3wySyQ4T7qz9s7g for ; Thu, 29 Jun 2017 02:33:02 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752152AbdF1Qcv (ORCPT ); Wed, 28 Jun 2017 12:32:51 -0400 Received: from metis.ext.4.pengutronix.de ([92.198.50.35]:46293 "EHLO metis.ext.4.pengutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752145AbdF1Qcj (ORCPT ); Wed, 28 Jun 2017 12:32:39 -0400 Received: from dude.hi.pengutronix.de ([2001:67c:670:100:1d::7]) by metis.ext.pengutronix.de with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.84_2) (envelope-from ) id 1dQFtD-0007nA-HU; Wed, 28 Jun 2017 18:32:27 +0200 Received: from mgr by dude.hi.pengutronix.de with local (Exim 4.89) (envelope-from ) id 1dQFtC-00083y-IK; Wed, 28 Jun 2017 18:32:26 +0200 From: Michael Grzeschik To: davem@davemloft.net Cc: netdev@vger.kernel.org, kernel@pengutronix.de Subject: [PATCH 4/4] arcnet: com20020-pci: add support for PCIFB2 card Date: Wed, 28 Jun 2017 18:32:21 +0200 Message-Id: <20170628163221.32301-5-m.grzeschik@pengutronix.de> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170628163221.32301-1-m.grzeschik@pengutronix.de> References: <20170628163221.32301-1-m.grzeschik@pengutronix.de> X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::7 X-SA-Exim-Mail-From: mgr@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: netdev@vger.kernel.org Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org We add support for the PCIFB2 card from EAE. Beside other cards, this card has the backplane mode enabled by default. Signed-off-by: Michael Grzeschik --- drivers/net/arcnet/com20020-pci.c | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/drivers/net/arcnet/com20020-pci.c b/drivers/net/arcnet/com20020-pci.c index f5854ab7dc326..24deb88a37f06 100644 --- a/drivers/net/arcnet/com20020-pci.c +++ b/drivers/net/arcnet/com20020-pci.c @@ -201,6 +201,9 @@ static int com20020pci_probe(struct pci_dev *pdev, lp->backplane = (inb(priv->misc) >> (2 + i)) & 0x1; + if (!strncmp(ci->name, "EAE PLX-PCI FB2", 15)) + lp->backplane = 1; + /* Get the dev_id from the PLX rotary coder */ if (!strncmp(ci->name, "EAE PLX-PCI MA1", 15)) dev->dev_id = 0xc; @@ -385,6 +388,31 @@ static struct com20020_pci_card_info card_info_eae_ma1 = { .flags = ARC_CAN_10MBIT, }; +static struct com20020_pci_card_info card_info_eae_fb2 = { + .name = "EAE PLX-PCI FB2", + .devcount = 1, + .chan_map_tbl = { + { + .bar = 2, + .offset = 0x00, + .size = 0x08, + }, + }, + .misc_map = { + .bar = 2, + .offset = 0x10, + .size = 0x04, + }, + .leds = { + { + .green = 0x0, + .red = 0x1, + }, + }, + .rotary = 0x0, + .flags = ARC_CAN_10MBIT, +}; + static const struct pci_device_id com20020pci_id_table[] = { { 0x1571, 0xa001, @@ -531,6 +559,12 @@ static const struct pci_device_id com20020pci_id_table[] = { (kernel_ulong_t)&card_info_eae_ma1 }, { + 0x10B5, 0x9050, + 0x10B5, 0x3294, + 0, 0, + (kernel_ulong_t)&card_info_eae_fb2 + }, + { 0x14BA, 0x6000, PCI_ANY_ID, PCI_ANY_ID, 0, 0,