From patchwork Tue Mar 21 15:12:11 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 741627 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3vnc0T6kwdz9s2x for ; Wed, 22 Mar 2017 02:18:49 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="eyD8zFMo"; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932562AbdCUPSc (ORCPT ); Tue, 21 Mar 2017 11:18:32 -0400 Received: from mail-wm0-f65.google.com ([74.125.82.65]:34581 "EHLO mail-wm0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932478AbdCUPS3 (ORCPT ); Tue, 21 Mar 2017 11:18:29 -0400 Received: by mail-wm0-f65.google.com with SMTP id u132so3537290wmg.1; Tue, 21 Mar 2017 08:18:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=BUEXvVfwl9c3L7vr5m/k2aF+pnXEKCz0s99gEGK6kaM=; b=eyD8zFMoO+tGlhG/2wGxHnaFtCbdokL+FdI6mZBWtNubViMMEzcbH4dw1z0chq9MDH eKT1FFiOYPeTUcdkQH6zfnvXf6/oFiL0MLAwteMPH1Ir5ZJbkhyGn8ST/Vbg0fHlPdr6 chSf0uy0wOUiri+oUSC3vK+688I+dpYmyAhw4+mArMG2LsnE4XNsZDkS7q37X7bq9+um LitSEFKhflSA97AYOfgM1W2MUUjoKVgpXe2GM+sSqVSwnS7u8H5JFVjdMDGyotNSA+If BZlb7H/Cojr4yJfEDc8OGCYajbwGeXRQ2bpboEkD24/hxAJk+4odT+IlXrdBTAEA3i43 mxMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=BUEXvVfwl9c3L7vr5m/k2aF+pnXEKCz0s99gEGK6kaM=; b=E4bLRDRHaSmKsWcv+CFg10FqdinJ/ro2rMOXnBDM8IrCgcIALNW7V5DtJ5BCZzE4LY M/BVQx4Blny0wQwdevSgdToWGniDj8a6im2NeIQIX8IhGHMu5E1V2OSqp9bouNh86GTb 9NATUiTJPbJM2HIp+xBRRBWPorKuRzn99HXyepjva67uWpMCdlvGO+qPG/2FJx2Xk2eX evfmVYSDLTUedC+rKjo8GLhoAwTp3p45KxYdB3JixvMXdK8KB/10A2NyrgjTYvyDHbvB g7K7OTLfXkj2es6zyGqzxtyJw5hOJiuAu0+8Uk+l91Wnkt+PKFLgCMoISF2kydiSB6la 3aug== X-Gm-Message-State: AFeK/H1pdWHS/01oaPC8t5D2k1m601rVhWNpI3720WM8dy9VyWBQtYtc4NQXtaMcBR+JPw== X-Received: by 10.28.4.10 with SMTP id 10mr3170945wme.124.1490109135290; Tue, 21 Mar 2017 08:12:15 -0700 (PDT) Received: from localhost (port-52488.pppoe.wtnet.de. [46.59.205.174]) by smtp.gmail.com with ESMTPSA id h187sm2164788wma.32.2017.03.21.08.12.14 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 21 Mar 2017 08:12:14 -0700 (PDT) From: Thierry Reding To: "David S . Miller" Cc: Giuseppe Cavallaro , Alexandre Torgue , Joao Pinto , LABBE Corentin , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/3] net: stmmac: Use AVB mode by default Date: Tue, 21 Mar 2017 16:12:11 +0100 Message-Id: <20170321151211.31841-3-thierry.reding@gmail.com> X-Mailer: git-send-email 2.12.0 In-Reply-To: <20170321151211.31841-1-thierry.reding@gmail.com> References: <20170321151211.31841-1-thierry.reding@gmail.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Thierry Reding Prior to the recent multi-queue changes the driver would configure the queues to use the AVB mode, but the mode then got switched to DCB. The hardware still works fine in DCB mode, but my testing capabilities are limited, so it's safer to revert to the prior setting anyway. Signed-off-by: Thierry Reding Acked-By: Joao Pinto --- include/linux/stmmac.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h index be47b859e954..8349a5c1537b 100644 --- a/include/linux/stmmac.h +++ b/include/linux/stmmac.h @@ -56,8 +56,8 @@ #define MTL_RX_ALGORITHM_WSP 0x5 /* RX/TX Queue Mode */ -#define MTL_QUEUE_DCB 0x0 -#define MTL_QUEUE_AVB 0x1 +#define MTL_QUEUE_AVB 0x0 +#define MTL_QUEUE_DCB 0x1 /* The MDC clock could be set higher than the IEEE 802.3 * specified frequency limit 0f 2.5 MHz, by programming a clock divider