From patchwork Tue Mar 14 00:41:35 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Berger X-Patchwork-Id: 738508 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3vhwwl1q9Yz9s75 for ; Tue, 14 Mar 2017 11:44:23 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="JsxYGMzJ"; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753939AbdCNAmY (ORCPT ); Mon, 13 Mar 2017 20:42:24 -0400 Received: from mail-qk0-f195.google.com ([209.85.220.195]:35222 "EHLO mail-qk0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753689AbdCNAmU (ORCPT ); Mon, 13 Mar 2017 20:42:20 -0400 Received: by mail-qk0-f195.google.com with SMTP id o135so39365501qke.2; Mon, 13 Mar 2017 17:42:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=tFZpDpHAjxyZjY8qonv6EnKjx661DLQY0yvkAtDG0q4=; b=JsxYGMzJ0L2FnwPNCYCy+76yGBwHxWQdPY7VT88wbRkgpyU1IIKdDEE1w7/b74ehAY pKSXEj7n5FilXe19RNSuf2+wqwIH11g188QzqFx4Q6sPRs9Q7Qk+VlIfgZIV5xYJdozI tWobTu3/5JZo3NrYDugikk8Qad7rtgQp56uzi2yDbPvSoKBqmDEjW2jzMEmTKCBbMtYi dCjD/bQsrG1OE45GBqUwdOkA1DXYETNrzL6JXACuqDAUzy1/t6Mg8iv6GqOr3MtYwU8G aW11HKQ/JkiivJpXryb+FYXSPZNS6rm8tX1KRJmOZkFzmKV7xtGkSN4bOt5c43oFy2N3 Hl4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=tFZpDpHAjxyZjY8qonv6EnKjx661DLQY0yvkAtDG0q4=; b=c6l0G+5ZaKbc9ymFeiSyVBWtvtj1sCeDmXATyYvmDzhANr5ArcNW78U21DqkVH1RpK hoyRIL+bhpDxKkHVHOgd3RcvRrWs1c46u9v4g9l1tr76huIjlFHF9fgC4eJnz31HUm94 Svao0ylFgcrrKyKGASfDSgh1kmlXjsU8pWj15vFUqiBZiGqD/+cCMvoZRq1DfVn/55Tl kcwzg1Lx7dovTk7Ht14W1EmubbPqffcue2FD1GmV3DeVnxGL8Qun95BLgiyHuJYzybYj m3MDo06xmdAmIYBzgHBE67AO3HVZrXWHtQGU9K2nu2NILZy9dRQCMowMbLjun8ZpPeLo aZbQ== X-Gm-Message-State: AFeK/H2kWK/JB2kpdSUT5lV77IBmBbJNuxtPYBdzrjL8GJ3I+ejqq9hoPk5oARleRm6N6A== X-Received: by 10.55.92.195 with SMTP id q186mr3677164qkb.84.1489452134076; Mon, 13 Mar 2017 17:42:14 -0700 (PDT) Received: from stb-bld-02.irv.broadcom.com ([192.19.255.250]) by smtp.gmail.com with ESMTPSA id y52sm13353343qty.60.2017.03.13.17.42.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 13 Mar 2017 17:42:13 -0700 (PDT) From: Doug Berger To: f.fainelli@gmail.com Cc: robh+dt@kernel.org, mark.rutland@arm.com, davem@davemloft.net, rafal@milecki.pl, xow@google.com, joel@jms.id.au, jon.mason@broadcom.com, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, pgynther@google.com, jaedon.shin@gmail.com, Doug Berger Subject: [PATCH net-next 05/12] net: bcmgenet: manage dma interrupts in napi code Date: Mon, 13 Mar 2017 17:41:35 -0700 Message-Id: <20170314004142.4746-6-opendmb@gmail.com> X-Mailer: git-send-email 2.11.1 In-Reply-To: <20170314004142.4746-1-opendmb@gmail.com> References: <20170314004142.4746-1-opendmb@gmail.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org This commit moves DMA interrupt enabling out of init_umac() and adds the masking of these interrupts to the napi enable and disable code. Signed-off-by: Doug Berger Reviewed-by: Florian Fainelli --- drivers/net/ethernet/broadcom/genet/bcmgenet.c | 39 +++++++++++++++----------- 1 file changed, 22 insertions(+), 17 deletions(-) diff --git a/drivers/net/ethernet/broadcom/genet/bcmgenet.c b/drivers/net/ethernet/broadcom/genet/bcmgenet.c index 22c92f5a9829..9be884021679 100644 --- a/drivers/net/ethernet/broadcom/genet/bcmgenet.c +++ b/drivers/net/ethernet/broadcom/genet/bcmgenet.c @@ -1862,8 +1862,6 @@ static int init_umac(struct bcmgenet_priv *priv) int ret; u32 reg; u32 int0_enable = 0; - u32 int1_enable = 0; - int i; dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n"); @@ -1890,12 +1888,6 @@ static int init_umac(struct bcmgenet_priv *priv) bcmgenet_intr_disable(priv); - /* Enable Rx default queue 16 interrupts */ - int0_enable |= UMAC_IRQ_RXDMA_DONE; - - /* Enable Tx default queue 16 interrupts */ - int0_enable |= UMAC_IRQ_TXDMA_DONE; - /* Configure backpressure vectors for MoCA */ if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) { reg = bcmgenet_bp_mc_get(priv); @@ -1913,16 +1905,7 @@ static int init_umac(struct bcmgenet_priv *priv) if (priv->hw_params->flags & GENET_HAS_MDIO_INTR) int0_enable |= (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR); - /* Enable Rx priority queue interrupts */ - for (i = 0; i < priv->hw_params->rx_queues; ++i) - int1_enable |= (1 << (UMAC_IRQ1_RX_INTR_SHIFT + i)); - - /* Enable Tx priority queue interrupts */ - for (i = 0; i < priv->hw_params->tx_queues; ++i) - int1_enable |= (1 << i); - bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); - bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR); dev_dbg(kdev, "done init umac\n"); @@ -2055,22 +2038,33 @@ static void bcmgenet_init_tx_napi(struct bcmgenet_priv *priv) static void bcmgenet_enable_tx_napi(struct bcmgenet_priv *priv) { unsigned int i; + u32 int0_enable = UMAC_IRQ_TXDMA_DONE; + u32 int1_enable = 0; struct bcmgenet_tx_ring *ring; for (i = 0; i < priv->hw_params->tx_queues; ++i) { ring = &priv->tx_rings[i]; napi_enable(&ring->napi); + int1_enable |= (1 << i); } ring = &priv->tx_rings[DESC_INDEX]; napi_enable(&ring->napi); + + bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); + bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR); } static void bcmgenet_disable_tx_napi(struct bcmgenet_priv *priv) { unsigned int i; + u32 int0_disable = UMAC_IRQ_TXDMA_DONE; + u32 int1_disable = 0xffff; struct bcmgenet_tx_ring *ring; + bcmgenet_intrl2_0_writel(priv, int0_disable, INTRL2_CPU_MASK_SET); + bcmgenet_intrl2_1_writel(priv, int1_disable, INTRL2_CPU_MASK_SET); + for (i = 0; i < priv->hw_params->tx_queues; ++i) { ring = &priv->tx_rings[i]; napi_disable(&ring->napi); @@ -2183,22 +2177,33 @@ static void bcmgenet_init_rx_napi(struct bcmgenet_priv *priv) static void bcmgenet_enable_rx_napi(struct bcmgenet_priv *priv) { unsigned int i; + u32 int0_enable = UMAC_IRQ_RXDMA_DONE; + u32 int1_enable = 0; struct bcmgenet_rx_ring *ring; for (i = 0; i < priv->hw_params->rx_queues; ++i) { ring = &priv->rx_rings[i]; napi_enable(&ring->napi); + int1_enable |= (1 << (UMAC_IRQ1_RX_INTR_SHIFT + i)); } ring = &priv->rx_rings[DESC_INDEX]; napi_enable(&ring->napi); + + bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); + bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR); } static void bcmgenet_disable_rx_napi(struct bcmgenet_priv *priv) { unsigned int i; + u32 int0_disable = UMAC_IRQ_RXDMA_DONE; + u32 int1_disable = 0xffff << UMAC_IRQ1_RX_INTR_SHIFT; struct bcmgenet_rx_ring *ring; + bcmgenet_intrl2_0_writel(priv, int0_disable, INTRL2_CPU_MASK_SET); + bcmgenet_intrl2_1_writel(priv, int1_disable, INTRL2_CPU_MASK_SET); + for (i = 0; i < priv->hw_params->rx_queues; ++i) { ring = &priv->rx_rings[i]; napi_disable(&ring->napi);