From patchwork Fri Mar 10 16:34:59 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 737468 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3vftGY0CCTz9s7t for ; Sat, 11 Mar 2017 03:37:41 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="DdZ4K0SW"; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933921AbdCJQhf (ORCPT ); Fri, 10 Mar 2017 11:37:35 -0500 Received: from mail-wm0-f66.google.com ([74.125.82.66]:33019 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933235AbdCJQfT (ORCPT ); Fri, 10 Mar 2017 11:35:19 -0500 Received: by mail-wm0-f66.google.com with SMTP id n11so3126435wma.0; Fri, 10 Mar 2017 08:35:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=MiAxQ1Ulypauobyw77uQGycAgy4aAB3wROLAf0z/xLI=; b=DdZ4K0SW6C/NwMauJYwitxJU5uU8Wdb+gOE6KrQSUAU9NC8eOFkBe3wamMMG2EGvMC T4hA+tWpdSxClnI1AswTKaSnWLXpkQBsx3oXuKjbLaMiMKDF2Lr4GM9CghwZY5/GfFfs 2mdAeMjuAxLVXDNZKs6Q8qahFJMdG866O6H+UDwLDaoMGB15oy2P8c+EsSdjJcGNrLf1 pPVLd5Q6nN5dxe/+1nJdach5reQNmgJpGxfS5HJBuFOCwD47POEbt1c3yMrrYQegBm+h u5jiEVuuSyDUi4pN/iOEgw6fuZXRzYLwZzxPERtmj8nz+d7j+WR640xjedPrHXxto89/ oJCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=MiAxQ1Ulypauobyw77uQGycAgy4aAB3wROLAf0z/xLI=; b=SoigIhjcsk77fhg3P1gFuo0y376lVnCQvYjj54rXl8jjCqJXd/cTXTUBebbetKm/DM 1kcZPbYjKcmhZZ5rUbZjNGntYlcJ9vPAZQFepIvxtben15Ce4duykVfanvsTos2xwGqK rRHnjuAWh6+LtJJkw17Ch47RNSLHacQTxdVr7JuJMqcjWiqesPgTQ9XaBzzdG+rs9/mQ f/ougp72C6MmhoD8Dj+04+TnrmxX+A62WZiJzIUO0tRhc2v0RWHoOX/fHt0pEKJcga4v a+knyThLoUmjAmgbTU4YCDLhnzoSth/HRUnjUUECaxWNv1ScwVnY6JPnOZvA595HQyVl KRVQ== X-Gm-Message-State: AFeK/H2g8D6G+8Uu0dxT9HKz7TIlmZ79PaiXeZVf3TeZLc80dxON9W09brmDG7G+kW6Ogw== X-Received: by 10.28.148.143 with SMTP id w137mr3241085wmd.72.1489163716210; Fri, 10 Mar 2017 08:35:16 -0800 (PST) Received: from localhost (port-55061.pppoe.wtnet.de. [46.59.215.197]) by smtp.gmail.com with ESMTPSA id u7sm13562175wru.56.2017.03.10.08.35.14 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 10 Mar 2017 08:35:14 -0800 (PST) From: Thierry Reding To: "David S . Miller" Cc: Giuseppe Cavallaro , Alexandre Torgue , Joao Pinto , Jon Hunter , Mikko Perttunen , netdev@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 7/9] net: stmmac: Program RX queue size and flow control Date: Fri, 10 Mar 2017 17:34:59 +0100 Message-Id: <20170310163501.31811-8-thierry.reding@gmail.com> X-Mailer: git-send-email 2.12.0 In-Reply-To: <20170310163501.31811-1-thierry.reding@gmail.com> References: <20170310163501.31811-1-thierry.reding@gmail.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Thierry Reding Program the receive queue size based on the RX FIFO size and enable hardware flow control for large FIFOs. Signed-off-by: Thierry Reding --- Changes in v2: - add comments to clarify flow control threshold programming drivers/net/ethernet/stmicro/stmmac/dwmac4.h | 12 ++++++ drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c | 52 +++++++++++++++++++++++- 2 files changed, 62 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h index 83f5e953e291..3b1828b4d294 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h @@ -182,6 +182,7 @@ enum power_event { #define MTL_OP_MODE_TSF BIT(1) #define MTL_OP_MODE_TQS_MASK GENMASK(24, 16) +#define MTL_OP_MODE_TQS_SHIFT 16 #define MTL_OP_MODE_TTC_MASK 0x70 #define MTL_OP_MODE_TTC_SHIFT 4 @@ -195,6 +196,17 @@ enum power_event { #define MTL_OP_MODE_TTC_384 (6 << MTL_OP_MODE_TTC_SHIFT) #define MTL_OP_MODE_TTC_512 (7 << MTL_OP_MODE_TTC_SHIFT) +#define MTL_OP_MODE_RQS_MASK GENMASK(29, 20) +#define MTL_OP_MODE_RQS_SHIFT 20 + +#define MTL_OP_MODE_RFD_MASK GENMASK(19, 14) +#define MTL_OP_MODE_RFD_SHIFT 14 + +#define MTL_OP_MODE_RFA_MASK GENMASK(13, 8) +#define MTL_OP_MODE_RFA_SHIFT 8 + +#define MTL_OP_MODE_EHFC BIT(7) + #define MTL_OP_MODE_RTC_MASK 0x18 #define MTL_OP_MODE_RTC_SHIFT 3 diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c index 55270933bae1..6ac6b2600a7c 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c @@ -183,8 +183,9 @@ static void dwmac4_rx_watchdog(void __iomem *ioaddr, u32 riwt) } static void dwmac4_dma_chan_op_mode(void __iomem *ioaddr, int txmode, - int rxmode, u32 channel) + int rxmode, u32 channel, int rxfifosz) { + unsigned int rqs = rxfifosz / 256 - 1; u32 mtl_tx_op, mtl_rx_op, mtl_rx_int; /* Following code only done for channel 0, other channels not yet @@ -250,6 +251,53 @@ static void dwmac4_dma_chan_op_mode(void __iomem *ioaddr, int txmode, mtl_rx_op |= MTL_OP_MODE_RTC_128; } + mtl_rx_op &= ~MTL_OP_MODE_RQS_MASK; + mtl_rx_op |= rqs << MTL_OP_MODE_RQS_SHIFT; + + /* enable flow control only if each channel gets 4 KiB or more FIFO */ + if (rxfifosz >= 4096) { + unsigned int rfd, rfa; + + mtl_rx_op |= MTL_OP_MODE_EHFC; + + /* Set Threshold for Activating Flow Control to min 2 frames, + * i.e. 1500 * 2 = 3000 bytes. + * + * Set Threshold for Deactivating Flow Control to min 1 frame, + * i.e. 1500 bytes. + */ + switch (rxfifosz) { + case 4096: + /* This violates the above formula because of FIFO size + * limit therefore overflow may occur in spite of this. + */ + rfd = 0x03; /* Full-2.5K */ + rfa = 0x01; /* Full-1.5K */ + break; + + case 8192: + rfd = 0x06; /* Full-4K */ + rfa = 0x0a; /* Full-6K */ + break; + + case 16384: + rfd = 0x06; /* Full-4K */ + rfa = 0x12; /* Full-10K */ + break; + + default: + rfd = 0x06; /* Full-4K */ + rfa = 0x1e; /* Full-16K */ + break; + } + + mtl_rx_op &= ~MTL_OP_MODE_RFD_MASK; + mtl_rx_op |= rfd << MTL_OP_MODE_RFD_SHIFT; + + mtl_rx_op &= ~MTL_OP_MODE_RFA_MASK; + mtl_rx_op |= rfa << MTL_OP_MODE_RFA_SHIFT; + } + writel(mtl_rx_op, ioaddr + MTL_CHAN_RX_OP_MODE(channel)); /* Enable MTL RX overflow */ @@ -262,7 +310,7 @@ static void dwmac4_dma_operation_mode(void __iomem *ioaddr, int txmode, int rxmode, int rxfifosz) { /* Only Channel 0 is actually configured and used */ - dwmac4_dma_chan_op_mode(ioaddr, txmode, rxmode, 0); + dwmac4_dma_chan_op_mode(ioaddr, txmode, rxmode, 0, rxfifosz); } static void dwmac4_get_hw_feature(void __iomem *ioaddr,