From patchwork Thu Feb 23 17:24:36 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 731626 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3vTh365SWYz9s7d for ; Fri, 24 Feb 2017 04:25:54 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="dr2rvHgF"; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751548AbdBWRZ3 (ORCPT ); Thu, 23 Feb 2017 12:25:29 -0500 Received: from mail-wr0-f194.google.com ([209.85.128.194]:36052 "EHLO mail-wr0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751190AbdBWRZA (ORCPT ); Thu, 23 Feb 2017 12:25:00 -0500 Received: by mail-wr0-f194.google.com with SMTP id z61so4623863wrc.3; Thu, 23 Feb 2017 09:24:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=hA4eflCMXyyUVtx8y4jJHbEk9a77JRDPSfvEBx1Cx68=; b=dr2rvHgFCjqP2mtHGg6InQ65niA+u8eM4gyN8lyMdHvwVFjBW9df+2cBpzFgxhuqMT 0h1eK1aeqUsZ4fhVFrdy/ksexFOZQ2C+AQBjBRi0Vo9UZN38aW8sTDha7fWWk9s75Q9+ UDHjl065VCwIWwbezMCS6pe1+pwyMufOmWL201+hOHCKuAM3/qjOWUtvFS6CpK0mmAMP Vk9SOToKk7HZMyOS+gc5eqRdZ1AT0rij8pGbtVShYsNoHrvGZ5uSVAo5n8rGgMuo2xDR Nk6NiEWEaTpwsIMlP2VzxLRDoNCJoTYsf9lCVijDhY1IvzA5PcwFmBiyVorXgQtzlcp0 B1/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=hA4eflCMXyyUVtx8y4jJHbEk9a77JRDPSfvEBx1Cx68=; b=OaB3OyVoVIgOvGYl8SVeEfNFL89Tj43F6lGlPaQ2A1Xw2P+hON44/dvQHwlrHjPDNX hxNuOo8z67OFIYYt4qTjl46dUkQOq4FOoWqKTsrR2BnWA1TggBEFkjcA1UUspeQYaE7p DvdLEmZd5AFEVFRf8ghGJibyMOvpX9D5yVAbKlHnnSv/spvEafazoG9TGqXAtGBjqUH1 Wr54V6DjinHj0jGZ1j7KHUBzkN9Xs7GrNMojSRSbQRKE1MskSSu4xlv5l8ietW8hr037 SWm1Y4cEOUrDXabNg5OQFPQtXPbxOG2n+RNtMekgmacp5jt3YogTiKdaHChJ356ir4Gf j90g== X-Gm-Message-State: AMke39nLGuCsedYGZCi10moDUyZWaJW9uOb61OcsHPiJ0ywl5c1SZTEWcb2tQIhSqerWSQ== X-Received: by 10.223.181.129 with SMTP id c1mr15022644wre.147.1487870689542; Thu, 23 Feb 2017 09:24:49 -0800 (PST) Received: from localhost (port-435.pppoe.wtnet.de. [84.46.1.180]) by smtp.gmail.com with ESMTPSA id i15sm7597987wmf.21.2017.02.23.09.24.48 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 23 Feb 2017 09:24:48 -0800 (PST) From: Thierry Reding To: "David S . Miller" Cc: Giuseppe Cavallaro , Alexandre Torgue , Rob Herring , Mark Rutland , Joao Pinto , Alexandre Courbot , Jon Hunter , netdev@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/7] net: stmmac: Program RX queue size and flow control Date: Thu, 23 Feb 2017 18:24:36 +0100 Message-Id: <20170223172438.14770-6-thierry.reding@gmail.com> X-Mailer: git-send-email 2.11.1 In-Reply-To: <20170223172438.14770-1-thierry.reding@gmail.com> References: <20170223172438.14770-1-thierry.reding@gmail.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Thierry Reding Program the receive queue size based on the RX FIFO size and enable hardware flow control for large FIFOs. Signed-off-by: Thierry Reding --- drivers/net/ethernet/stmicro/stmmac/dwmac4.h | 12 +++++++ drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c | 43 ++++++++++++++++++++++-- 2 files changed, 53 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h index db45134fddf0..9acc1f1252b3 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h @@ -180,6 +180,7 @@ enum power_event { #define MTL_OP_MODE_TSF BIT(1) #define MTL_OP_MODE_TQS_MASK GENMASK(24, 16) +#define MTL_OP_MODE_TQS_SHIFT 16 #define MTL_OP_MODE_TTC_MASK 0x70 #define MTL_OP_MODE_TTC_SHIFT 4 @@ -193,6 +194,17 @@ enum power_event { #define MTL_OP_MODE_TTC_384 (6 << MTL_OP_MODE_TTC_SHIFT) #define MTL_OP_MODE_TTC_512 (7 << MTL_OP_MODE_TTC_SHIFT) +#define MTL_OP_MODE_RQS_MASK GENMASK(29, 20) +#define MTL_OP_MODE_RQS_SHIFT 20 + +#define MTL_OP_MODE_RFD_MASK GENMASK(19, 14) +#define MTL_OP_MODE_RFD_SHIFT 14 + +#define MTL_OP_MODE_RFA_MASK GENMASK(13, 8) +#define MTL_OP_MODE_RFA_SHIFT 8 + +#define MTL_OP_MODE_EHFC BIT(7) + #define MTL_OP_MODE_RTC_MASK 0x18 #define MTL_OP_MODE_RTC_SHIFT 3 diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c index 8d249f3b34c8..03d230201960 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c @@ -185,8 +185,9 @@ static void dwmac4_rx_watchdog(void __iomem *ioaddr, u32 riwt) } static void dwmac4_dma_chan_op_mode(void __iomem *ioaddr, int txmode, - int rxmode, u32 channel) + int rxmode, u32 channel, int rxfifosz) { + unsigned int rqs = rxfifosz / 256 - 1; u32 mtl_tx_op, mtl_rx_op, mtl_rx_int; /* Following code only done for channel 0, other channels not yet @@ -252,6 +253,44 @@ static void dwmac4_dma_chan_op_mode(void __iomem *ioaddr, int txmode, mtl_rx_op |= MTL_OP_MODE_RTC_128; } + mtl_rx_op &= ~MTL_OP_MODE_RQS_MASK; + mtl_rx_op |= rqs << MTL_OP_MODE_RQS_SHIFT; + + /* enable flow control only if each channel gets 4 KiB or more FIFO */ + if (rxfifosz >= 4096) { + unsigned int rfd, rfa; + + mtl_rx_op |= MTL_OP_MODE_EHFC; + + switch (rxfifosz) { + case 4096: + rfd = 0x03; + rfa = 0x01; + break; + + case 8192: + rfd = 0x06; + rfa = 0x0a; + break; + + case 16384: + rfd = 0x06; + rfa = 0x12; + break; + + default: + rfd = 0x06; + rfa = 0x1e; + break; + } + + mtl_rx_op &= ~MTL_OP_MODE_RFD_MASK; + mtl_rx_op |= rfd << MTL_OP_MODE_RFD_SHIFT; + + mtl_rx_op &= ~MTL_OP_MODE_RFA_MASK; + mtl_rx_op |= rfa << MTL_OP_MODE_RFA_SHIFT; + } + writel(mtl_rx_op, ioaddr + MTL_CHAN_RX_OP_MODE(channel)); /* Enable MTL RX overflow */ @@ -264,7 +303,7 @@ static void dwmac4_dma_operation_mode(void __iomem *ioaddr, int txmode, int rxmode, int rxfifosz) { /* Only Channel 0 is actually configured and used */ - dwmac4_dma_chan_op_mode(ioaddr, txmode, rxmode, 0); + dwmac4_dma_chan_op_mode(ioaddr, txmode, rxmode, 0, rxfifosz); } static void dwmac4_get_hw_feature(void __iomem *ioaddr,