Message ID | 20161115221115.12403.53949.stgit@tlendack-t1.amdoffice.net |
---|---|
State | Accepted, archived |
Delegated to: | David Miller |
Headers | show
Return-Path: <netdev-owner@vger.kernel.org> X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3tJM6y6Hhzz9t0m for <patchwork-incoming@ozlabs.org>; Wed, 16 Nov 2016 09:11:38 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=amdcloud.onmicrosoft.com header.i=@amdcloud.onmicrosoft.com header.b="DipF0BPA"; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1161010AbcKOWL3 (ORCPT <rfc822;patchwork-incoming@ozlabs.org>); Tue, 15 Nov 2016 17:11:29 -0500 Received: from mail-cys01nam02on0081.outbound.protection.outlook.com ([104.47.37.81]:36682 "EHLO NAM02-CY1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S935038AbcKOWLZ (ORCPT <rfc822;netdev@vger.kernel.org>); Tue, 15 Nov 2016 17:11:25 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector1-amd-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=dWAnUVYfOQwbTjcVhXM8v3FxOMEw9LFnxfmcmH5abdo=; b=DipF0BPAba25A6efnvIN0GM0qkOw2PlSNMASKuYZc0XdcZn+87qh8012hyvQx2Axm9pD14kbauC5DXcygvs1w9OVrWzGHITW4usvlqzD9Amcf6aWg9DSHyhGeGtde28woIeSWlWLiRsbpwRomKfKyj6olB3KCHGECqGnGgqA8DQ= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Thomas.Lendacky@amd.com; Received: from tlendack-t1.amdoffice.net (165.204.78.1) by MWHPR12MB1151.namprd12.prod.outlook.com (10.169.204.15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id 15.1.721.10; Tue, 15 Nov 2016 22:11:20 +0000 From: Tom Lendacky <thomas.lendacky@amd.com> Subject: [PATCH net-next 2/2] amd-xgbe: Fix maximum GPIO value check To: <netdev@vger.kernel.org> CC: <colin.king@canonical.com>, David Miller <davem@davemloft.net>, <dan.carpenter@oracle.com> Date: Tue, 15 Nov 2016 16:11:15 -0600 Message-ID: <20161115221115.12403.53949.stgit@tlendack-t1.amdoffice.net> In-Reply-To: <20161115221055.12403.90574.stgit@tlendack-t1.amdoffice.net> References: <20161115221055.12403.90574.stgit@tlendack-t1.amdoffice.net> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Content-Type: text/plain; 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diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-dev.c b/drivers/net/ethernet/amd/xgbe/xgbe-dev.c index 30056e2..aaf0350 100644 --- a/drivers/net/ethernet/amd/xgbe/xgbe-dev.c +++ b/drivers/net/ethernet/amd/xgbe/xgbe-dev.c @@ -1099,7 +1099,7 @@ static int xgbe_clr_gpio(struct xgbe_prv_data *pdata, unsigned int gpio) { unsigned int reg; - if (gpio > 16) + if (gpio > 15) return -EINVAL; reg = XGMAC_IOREAD(pdata, MAC_GPIOSR); @@ -1114,7 +1114,7 @@ static int xgbe_set_gpio(struct xgbe_prv_data *pdata, unsigned int gpio) { unsigned int reg; - if (gpio > 16) + if (gpio > 15) return -EINVAL; reg = XGMAC_IOREAD(pdata, MAC_GPIOSR);
The GPIO support in the hardware allows for up to 16 GPIO pins, enumerated from 0 to 15. The driver uses the wrong value (16) to validate the GPIO pin range in the routines to set and clear the GPIO output pins. Update the code to use the correct value (15). Reported-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> --- drivers/net/ethernet/amd/xgbe/xgbe-dev.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)