diff mbox

sh_eth: R8A7740 supports packet shecksumming

Message ID 1871204.P0zXJRoIfd@wasted.cogentembedded.com
State Accepted, archived
Delegated to: David Miller
Headers show

Commit Message

Sergei Shtylyov Jan. 4, 2017, 9:29 p.m. UTC
The R8A7740 GEther controller supports the packet checksum offloading
but the 'hw_crc' (bad name, I'll fix it) flag isn't set in the R8A7740
data,  thus CSMR isn't cleared...

Fixes: 73a0d907301e ("net: sh_eth: add support R8A7740")
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

---
This patch is against DaveM's 'net.git' repo plus the fixes sent recently...

 drivers/net/ethernet/renesas/sh_eth.c |    1 +
 1 file changed, 1 insertion(+)

Comments

Sergei Shtylyov Jan. 5, 2017, 9:33 a.m. UTC | #1
Hello!

    Oops, typo in the subject, "shecksumming". David, should I resend?

MBR, Sergei
David Miller Jan. 6, 2017, 8:35 p.m. UTC | #2
From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Date: Thu, 05 Jan 2017 00:29:32 +0300

> The R8A7740 GEther controller supports the packet checksum offloading
> but the 'hw_crc' (bad name, I'll fix it) flag isn't set in the R8A7740
> data,  thus CSMR isn't cleared...
> 
> Fixes: 73a0d907301e ("net: sh_eth: add support R8A7740")
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

Applied.
David Miller Jan. 6, 2017, 8:35 p.m. UTC | #3
From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Date: Thu, 5 Jan 2017 12:33:21 +0300

>    Oops, typo in the subject, "shecksumming". David, should I resend?

I accidently pushed this out without fixing the typo, sorry about
that but that's going to be how it is I'm afraid :-)
diff mbox

Patch

Index: net/drivers/net/ethernet/renesas/sh_eth.c
===================================================================
--- net.orig/drivers/net/ethernet/renesas/sh_eth.c
+++ net/drivers/net/ethernet/renesas/sh_eth.c
@@ -574,6 +574,7 @@  static struct sh_eth_cpu_data r8a7740_da
 	.rpadir_value   = 2 << 16,
 	.no_trimd	= 1,
 	.no_ade		= 1,
+	.hw_crc		= 1,
 	.tsu		= 1,
 	.select_mii	= 1,
 	.shift_rd0	= 1,