diff mbox series

[net,4/7] net: stmmac: Fix priority steering for tx/rx queue >3

Message ID 1578967276-55956-5-git-send-email-boon.leong.ong@intel.com
State Changes Requested
Delegated to: David Miller
Headers show
Series net: stmmac: general fixes for Ethernet functionality | expand

Commit Message

Ong Boon Leong Jan. 14, 2020, 2:01 a.m. UTC 
From: Voon Weifeng <weifeng.voon@intel.com>

Fix MACRO function define for TX and RX user priority queue steering for
register masking and shifting.

Fixes: a8f5102af2a7 ("net: stmmac: TX and RX queue priority configuration")

Signed-off-by: Voon Weifeng <weifeng.voon@intel.com>
Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com>
---
 drivers/net/ethernet/stmicro/stmmac/dwmac4.h | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

Comments

Jose Abreu Jan. 13, 2020, 10:33 a.m. UTC | #1 
From: Ong Boon Leong <boon.leong.ong@intel.com>
Date: Jan/14/2020, 02:01:13 (UTC+00:00)

> Fix MACRO function define for TX and RX user priority queue steering for
> register masking and shifting.

I think this was already fixed as seen on:
- https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git/commit/?id=e8df7e8c233a18d2704e37ecff47583b494789d3

Did I forget something ?

---
Thanks,
Jose Miguel Abreu
Voon, Weifeng Jan. 14, 2020, 3:24 p.m. UTC | #2 
> > Fix MACRO function define for TX and RX user priority queue steering
> > for register masking and shifting.
> 
> I think this was already fixed as seen on:
> - https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-
> next.git/commit/?id=e8df7e8c233a18d2704e37ecff47583b494789d3
> 
> Did I forget something ?
This issue is indeed already fixed by the patch that you have pointed out.
Weifeng
diff mbox series

Patch

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h
index 2dc70d1..798a53a 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h
@@ -97,12 +97,14 @@ 
 #define GMAC_RX_FLOW_CTRL_RFE		BIT(0)
 
 /* RX Queues Priorities */
-#define GMAC_RXQCTRL_PSRQX_MASK(x)	GENMASK(7 + ((x) * 8), 0 + ((x) * 8))
-#define GMAC_RXQCTRL_PSRQX_SHIFT(x)	((x) * 8)
+#define GMAC_RXQCTRL_PSRQX_MASK(x)	GENMASK(7 + (((x) % 4) * 8), \
+						0 + (((x) % 4) * 8))
+#define GMAC_RXQCTRL_PSRQX_SHIFT(x)	(((x) % 4) * 8)
 
 /* TX Queues Priorities */
-#define GMAC_TXQCTRL_PSTQX_MASK(x)	GENMASK(7 + ((x) * 8), 0 + ((x) * 8))
-#define GMAC_TXQCTRL_PSTQX_SHIFT(x)	((x) * 8)
+#define GMAC_TXQCTRL_PSTQX_MASK(x)	GENMASK(7 + (((x) % 4) * 8), \
+						0 + (((x) % 4) * 8))
+#define GMAC_TXQCTRL_PSTQX_SHIFT(x)	(((x) % 4) * 8)
 
 /* MAC Flow Control TX */
 #define GMAC_TX_FLOW_CTRL_TFE		BIT(1)