From patchwork Sun Apr 28 06:30:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?QmlhbyBIdWFuZyAo6buE5b2qKQ==?= X-Patchwork-Id: 1092169 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=mediatek.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44sHwn5wk0z9s7T for ; Sun, 28 Apr 2019 16:30:49 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726574AbfD1Gam (ORCPT ); Sun, 28 Apr 2019 02:30:42 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:58095 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726488AbfD1Gaj (ORCPT ); Sun, 28 Apr 2019 02:30:39 -0400 X-UUID: 2405f04490dd4f998ad1f91febcb0757-20190428 X-UUID: 2405f04490dd4f998ad1f91febcb0757-20190428 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 375670593; Sun, 28 Apr 2019 14:30:33 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Sun, 28 Apr 2019 14:30:32 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Sun, 28 Apr 2019 14:30:31 +0800 From: Biao Huang To: Jose Abreu , CC: Giuseppe Cavallaro , Alexandre Torgue , Maxime Coquelin , Matthias Brugger , , , , , , , , Subject: [PATCH 6/6] stmmac: dwmac-mediatek: modify csr_clk value to fix mdio read/write fail Date: Sun, 28 Apr 2019 14:30:09 +0800 Message-ID: <1556433009-25759-7-git-send-email-biao.huang@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1556433009-25759-1-git-send-email-biao.huang@mediatek.com> References: <1556433009-25759-1-git-send-email-biao.huang@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The frequency of csr clock is 66.5MHz, so the csr_clk value should be 0. Modify the csr_clk value to fix mdio read/write fail issue. Signed-off-by: Biao Huang --- .../net/ethernet/stmicro/stmmac/dwmac-mediatek.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c index bf25629..6b12d0f 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c @@ -346,8 +346,8 @@ static int mediatek_dwmac_probe(struct platform_device *pdev) return PTR_ERR(plat_dat); plat_dat->interface = priv_plat->phy_mode; - /* clk_csr_i = 250-300MHz & MDC = clk_csr_i/124 */ - plat_dat->clk_csr = 5; + /* clk_csr_i = 60-100MHz & MDC = clk_csr_i/42 */ + plat_dat->clk_csr = 0; plat_dat->has_gmac4 = 1; plat_dat->has_gmac = 0; plat_dat->pmt = 0;