From patchwork Fri Nov 16 09:18:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?QmlhbyBIdWFuZyAo6buE5b2qKQ==?= X-Patchwork-Id: 998800 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=mediatek.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42xCNB1jWfz9sBQ for ; Fri, 16 Nov 2018 20:19:06 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389405AbeKPTa1 (ORCPT ); Fri, 16 Nov 2018 14:30:27 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:62775 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1727398AbeKPTa0 (ORCPT ); Fri, 16 Nov 2018 14:30:26 -0500 X-UUID: 5cb67d35a357418495ab0bc90dbba86b-20181116 X-UUID: 5cb67d35a357418495ab0bc90dbba86b-20181116 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 2124849772; Fri, 16 Nov 2018 17:18:54 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs03n1.mediatek.inc (172.21.101.181) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 16 Nov 2018 17:18:53 +0800 Received: from localhost.localdomain (10.17.3.153) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Fri, 16 Nov 2018 17:18:52 +0800 From: Biao Huang To: , CC: , , , , , , , , , , , , , Subject: [v3, PATCH 2/2] dt-binding: mediatek-dwmac: add binding document for MediaTek MT2712 DWMAC Date: Fri, 16 Nov 2018 17:18:46 +0800 Message-ID: <1542359926-28800-2-git-send-email-biao.huang@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1542359926-28800-1-git-send-email-biao.huang@mediatek.com> References: <1542359926-28800-1-git-send-email-biao.huang@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The commit adds the device tree binding documentation for the MediaTek DWMAC found on MediaTek MT2712. Change-Id: I3728666bf65927164bd82fa8dddb90df8270bd44 Signed-off-by: Biao Huang --- .../devicetree/bindings/net/mediatek-dwmac.txt | 77 ++++++++++++++++++++ 1 file changed, 77 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/mediatek-dwmac.txt diff --git a/Documentation/devicetree/bindings/net/mediatek-dwmac.txt b/Documentation/devicetree/bindings/net/mediatek-dwmac.txt new file mode 100644 index 0000000..7fd56e0 --- /dev/null +++ b/Documentation/devicetree/bindings/net/mediatek-dwmac.txt @@ -0,0 +1,77 @@ +MediaTek DWMAC glue layer controller + +This file documents platform glue layer for stmmac. +Please see stmmac.txt for the other unchanged properties. + +The device node has following properties. + +Required properties: +- compatible: Should be "mediatek,mt2712-gmac" for MT2712 SoC +- reg: Address and length of the register set for the device +- interrupts: Should contain the MAC interrupts +- interrupt-names: Should contain a list of interrupt names corresponding to + the interrupts in the interrupts property, if available. + Should be "macirq" for the main MAC IRQ +- clocks: Must contain a phandle for each entry in clock-names. +- clock-names: The name of the clock listed in the clocks property. These are + "axi", "apb", "mac_ext", "mac_parent", "ptp_ref", "ptp_parent", "ptp_top" + for MT2712 SoC +- mac-address: See ethernet.txt in the same directory +- phy-mode: See ethernet.txt in the same directory + +Optional properties: +- tx-delay: TX clock delay macro value. Range is 0~31. Default is 0. + It should be defined for rgmii/rgmii-rxid/mii interface. +- rx-delay: RX clock delay macro value. Range is 0~31. Default is 0. + It should be defined for rgmii/rgmii-txid/mii/rmii interface. +- fine-tune: This property will select coarse-tune delay or fine delay + for rgmii interface. + If fine-tune delay is enabled, tx-delay/rx-delay is 170+/-50ps + per stage. + Else coarse-tune delay is enabled, tx-delay/rx-delay is 0.55+/-0.2ns + per stage. + This property do not apply to non-rgmii PHYs. + Only coarse-tune delay is supported for mii/rmii PHYs. +- rmii-rxc: Reference clock of rmii is from external PHYs, + and it can be connected to TXC or RXC pin on MT2712 SoC. + If ref_clk <--> TXC, disable it. + Else ref_clk <--> RXC, enable it. +- txc-inverse: Inverse tx clock for mii/rgmii. + Inverse tx clock inside MAC relative to reference clock for rmii, + and it rarely happen. +- rxc-inverse: Inverse rx clock for mii/rgmii interfaces. + Inverse reference clock for rmii. + +Example: + eth: ethernet@1101c000 { + compatible = "mediatek,mt2712-gmac"; + reg = <0 0x1101c000 0 0x1300>; + interrupts = ; + interrupt-names = "macirq"; + phy-mode ="rgmii-id"; + mac-address = [00 55 7b b5 7d f7]; + clock-names = "axi", + "apb", + "mac_ext", + "mac_parent", + "ptp_ref", + "ptp_parent", + "ptp_top"; + clocks = <&pericfg CLK_PERI_GMAC>, + <&pericfg CLK_PERI_GMAC_PCLK>, + <&topckgen CLK_TOP_ETHER_125M_SEL>, + <&topckgen CLK_TOP_ETHERPLL_125M>, + <&topckgen CLK_TOP_ETHER_50M_SEL>, + <&topckgen CLK_TOP_APLL1_D3>, + <&topckgen CLK_TOP_APLL1>; + snps,txpbl = <32>; + snps,rxpbl = <32>; + snps,reset-gpio = <&pio 87 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + tx-delay = <9>; + rx-delay = <9>; + fine-tune; + rmii-rxc; + txc-inverse; + rxc-inverse; + };