From patchwork Tue May 22 11:16:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TWljaGFsIFZva8OhxI0=?= X-Patchwork-Id: 918169 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="fmjBl0Iy"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40qtRj42wXz9s5w for ; Tue, 22 May 2018 21:18:09 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751587AbeEVLSG (ORCPT ); Tue, 22 May 2018 07:18:06 -0400 Received: from mail-wm0-f66.google.com ([74.125.82.66]:35182 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751369AbeEVLRr (ORCPT ); Tue, 22 May 2018 07:17:47 -0400 Received: by mail-wm0-f66.google.com with SMTP id o78-v6so32541116wmg.0; Tue, 22 May 2018 04:17:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TYdUZdzqRG3vSXBb6JqH862O21/KZNzl8iS109rELPU=; b=fmjBl0Iye2KbfIeprptIQi2M/fB+a+g4NWIdjgfatmH9a3zWeOEucs229BI4fliZIw EXZWSkIg00DekBQoqXZm+Y12tIylhM2ibzMnm9UknFmQpAv2ZLb3qworivMGQQrPt2ee rmmooj1jfCbFRTl3MY9/5z6INYoDh3tSrmjs/vgE7i0GmZOtOHYt8dl5p5MH+7n9rILD IfjOcvrjZY2IPaqfIeEst3VY5KRXX8cusTaqywZT4ZD3+SxENlqej8UdyI2L6taby52i FHZSk/22YbnVArT6KOg3udAxxJUcmq4TIr2VFoFhYHPQbnwAhkfoqqwajry+9QLPXN36 UMrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TYdUZdzqRG3vSXBb6JqH862O21/KZNzl8iS109rELPU=; b=DyqhZDeRfzAIWpGqOu0rbR7ncOzHIYzYSTYZHjoVEbZbXZTlIw79cKXq4OeoIosw9F O9d8QyH4RlbXs5ncOJSlzYnFxdD7yN1+Jk2du2N0LpHaqHR317Za/RUfXzpF3X7U6jeX rDjwNqLHRXP/73dIZQPBdXeuYbqF9B8YobUT9vRJzBj5Kip5/F8jSmvCu4+qRzefuWt8 fa9uQYTlf88ICA4hgoJ2QspFiAMNj9CMABhK946prPaiugtDdT/Id4W5V4kL1LQMrb5L m25PfCLH0mxLiwXRQkASAlnzEQPDpTN9VgRr8u0cZk7i3TJyXoP8Buo8ebfFnCrX0qg8 iXZg== X-Gm-Message-State: ALKqPwdeoQFc1LZXR5rddnoVv7ZEiBulhhZ+CfUIYMcqdDU1l/xVNKdA i/5ADK3hQiip4AeTbRePHl0wdgxa X-Google-Smtp-Source: AB8JxZrvMmjl72Jt6aoWz9VsAbdTO/0EZDf/rI9wdjq3m7BAxPM9OXi6cMcA5eCbRs7bziP00UIuzw== X-Received: by 2002:a1c:7309:: with SMTP id d9-v6mr904643wmb.60.1526987865646; Tue, 22 May 2018 04:17:45 -0700 (PDT) Received: from iota-build.ysoft.local ([89.24.100.190]) by smtp.gmail.com with ESMTPSA id z2-v6sm15146747wmg.46.2018.05.22.04.17.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 22 May 2018 04:17:45 -0700 (PDT) From: "=?UTF-8?q?Michal=20Vok=C3=A1=C4=8D?=" X-Google-Original-From: =?utf-8?b?TWljaGFsIFZva8OhxI0=?= To: netdev@vger.kernel.org Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, f.fainelli@gmail.com, vivien.didelot@savoirfairelinux.com, andrew@lunn.ch, mark.rutland@arm.com, robh+dt@kernel.org, davem@davemloft.net, michal.vokac@ysoft.com Subject: [PATCH net-next v2 4/7] net: dsa: qca8k: Force CPU port to its highest bandwidth Date: Tue, 22 May 2018 13:16:29 +0200 Message-Id: <1526987792-56861-5-git-send-email-michal.vokac@ysoft.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1526987792-56861-1-git-send-email-michal.vokac@ysoft.com> References: <1526987792-56861-1-git-send-email-michal.vokac@ysoft.com> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org By default autonegotiation is enabled to configure MAC on all ports. For the CPU port autonegotiation can not be used so we need to set some sensible defaults manually. This patch forces the default setting of the CPU port to 1000Mbps/full duplex which is the chip maximum capability. Also correct size of the bit field used to configure link speed. Fixes: 6b93fb46480a ("net-next: dsa: add new driver for qca8xxx family") Signed-off-by: Michal Vokáč Reviewed-by: Andrew Lunn Reviewed-by: Florian Fainelli --- Changes in v2: - Add "Fixes" tag as pointed out by Florian. - Add "Reviewed-by" tags from Andrew and Florian. drivers/net/dsa/qca8k.c | 6 +++++- drivers/net/dsa/qca8k.h | 6 ++++-- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index 0d224f3..14a108b38 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -537,6 +537,7 @@ qca8k_setup(struct dsa_switch *ds) { struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; int ret, i, phy_mode = -1; + u32 mask; pr_debug("qca: setup\n"); @@ -564,7 +565,10 @@ qca8k_setup(struct dsa_switch *ds) if (ret < 0) return ret; - /* Enable CPU Port */ + /* Enable CPU Port, force it to maximum bandwidth and full-duplex */ + mask = QCA8K_PORT_STATUS_SPEED_1000 | QCA8K_PORT_STATUS_TXFLOW | + QCA8K_PORT_STATUS_RXFLOW | QCA8K_PORT_STATUS_DUPLEX; + qca8k_write(priv, QCA8K_REG_PORT_STATUS(QCA8K_CPU_PORT), mask); qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0, QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN); qca8k_port_set_status(priv, QCA8K_CPU_PORT, 1); diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h index 1cf8a92..5bda165 100644 --- a/drivers/net/dsa/qca8k.h +++ b/drivers/net/dsa/qca8k.h @@ -51,8 +51,10 @@ #define QCA8K_GOL_MAC_ADDR0 0x60 #define QCA8K_GOL_MAC_ADDR1 0x64 #define QCA8K_REG_PORT_STATUS(_i) (0x07c + (_i) * 4) -#define QCA8K_PORT_STATUS_SPEED GENMASK(2, 0) -#define QCA8K_PORT_STATUS_SPEED_S 0 +#define QCA8K_PORT_STATUS_SPEED GENMASK(1, 0) +#define QCA8K_PORT_STATUS_SPEED_10 0 +#define QCA8K_PORT_STATUS_SPEED_100 0x1 +#define QCA8K_PORT_STATUS_SPEED_1000 0x2 #define QCA8K_PORT_STATUS_TXMAC BIT(2) #define QCA8K_PORT_STATUS_RXMAC BIT(3) #define QCA8K_PORT_STATUS_TXFLOW BIT(4)