From patchwork Wed Mar 15 20:27:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Iyappan Subramanian X-Patchwork-Id: 739429 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3vk36G1gHcz9ryk for ; Thu, 16 Mar 2017 07:26:30 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=apm.com header.i=@apm.com header.b="Na2z2xfP"; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753777AbdCOU0M (ORCPT ); Wed, 15 Mar 2017 16:26:12 -0400 Received: from mail-pf0-f178.google.com ([209.85.192.178]:33313 "EHLO mail-pf0-f178.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751168AbdCOU0L (ORCPT ); Wed, 15 Mar 2017 16:26:11 -0400 Received: by mail-pf0-f178.google.com with SMTP id w189so13702105pfb.0 for ; Wed, 15 Mar 2017 13:26:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=apm.com; s=apm; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=kRIbl/Hs6Q03UJ+mUa+zmqdSWyh9wKxyy/mLjy4/GCc=; b=Na2z2xfP0YjaWPEoffhV99L3F6MQNmJQy33n+GXI6jOQHtPBrmZh6WpzJrfUOduha/ JSgUad3U/CD1RiJ/n7WdVMW+2xKyEEhwqbw1XtiM3JAE9ufI4dT3od1K+d6GenAGowqz 4tT8jLHKASX64ibFNX9RoVVwLqsnoeXBE7bMM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=kRIbl/Hs6Q03UJ+mUa+zmqdSWyh9wKxyy/mLjy4/GCc=; b=tbEekEeau82bsdbIZR3JMXuXDa7ASoCqh++O1HHU8I4hiYS/Yr7iXetSMXfEqrWjlN fgnr4G1O2LwQJEQelwNDIh85v+RlHdrlZycgymKD3QFkw359tbO4oy2zLUuZDQHHHVxt LLkkodprov/cERpcKd+eQ419Z8NuB2FabHi3EVkphX10oEQiT/fKZIrcVmparkZ4ocUy C6HEnvdPnptfqQwRnbb07itNqFm5FnGhPpJz7+vomhtAlIKm6IGoIqAN5//2PgofhX0O 01lLf0ddPPN+ytaw8Irz3N4e/0l6Gf644TJQcq4OYKn/4P0RzmM9jTtal+Qg0Mezurrg gwWA== X-Gm-Message-State: AFeK/H0HOn3VFPhK8yFMh5VbCEiDlxA2knKKSrMCw93QF82TeVEUG7KbpAuvuwX2OLX/D1xz X-Received: by 10.98.44.15 with SMTP id s15mr5832166pfs.161.1489609570337; Wed, 15 Mar 2017 13:26:10 -0700 (PDT) Received: from isubrama-dev.amcc.com ([206.80.4.98]) by smtp.gmail.com with ESMTPSA id r67sm5922281pfb.125.2017.03.15.13.26.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 15 Mar 2017 13:26:09 -0700 (PDT) From: Iyappan Subramanian To: davem@davemloft.net, netdev@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, patches@apm.com, kchudgar@apm.com, qnguyen@apm.com, Toan Le , Iyappan Subramanian Subject: [PATCH net-next 5/7] drivers: net: xgene: Add workaround for errata 10GE_1 Date: Wed, 15 Mar 2017 13:27:19 -0700 Message-Id: <1489609641-31557-6-git-send-email-isubramanian@apm.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1489609641-31557-1-git-send-email-isubramanian@apm.com> References: <1489609641-31557-1-git-send-email-isubramanian@apm.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Quan Nguyen This patch implements workaround for errata 10GE_1: 10Gb Ethernet port FIFO threshold default values are incorrect. Signed-off-by: Quan Nguyen Signed-off-by: Toan Le Signed-off-by: Iyappan Subramanian Tested-by: Fushen Chen --- drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.c | 7 +++++++ drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.h | 5 +++++ 2 files changed, 12 insertions(+) diff --git a/drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.c b/drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.c index ece19e6..423240c 100644 --- a/drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.c +++ b/drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.c @@ -341,8 +341,15 @@ static void xgene_xgmac_init(struct xgene_enet_pdata *pdata) xgene_enet_rd_csr(pdata, XG_RSIF_CONFIG_REG_ADDR, &data); data |= CFG_RSIF_FPBUFF_TIMEOUT_EN; + /* Errata 10GE_1 - FIFO threshold default value incorrect */ + RSIF_CLE_BUFF_THRESH_SET(&data, XG_RSIF_CLE_BUFF_THRESH); xgene_enet_wr_csr(pdata, XG_RSIF_CONFIG_REG_ADDR, data); + /* Errata 10GE_1 - FIFO threshold default value incorrect */ + xgene_enet_rd_csr(pdata, XG_RSIF_CONFIG1_REG_ADDR, &data); + RSIF_PLC_CLE_BUFF_THRESH_SET(&data, XG_RSIF_PLC_CLE_BUFF_THRESH); + xgene_enet_wr_csr(pdata, XG_RSIF_CONFIG1_REG_ADDR, data); + xgene_enet_rd_csr(pdata, XG_ENET_SPARE_CFG_REG_ADDR, &data); data |= BIT(12); xgene_enet_wr_csr(pdata, XG_ENET_SPARE_CFG_REG_ADDR, data); diff --git a/drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.h b/drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.h index 03b847a..e644a42 100644 --- a/drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.h +++ b/drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.h @@ -65,6 +65,11 @@ #define XG_DEF_PAUSE_THRES 0x390 #define XG_DEF_PAUSE_OFF_THRES 0x2c0 #define XG_RSIF_CONFIG_REG_ADDR 0x00a0 +#define XG_RSIF_CLE_BUFF_THRESH 0x3 +#define RSIF_CLE_BUFF_THRESH_SET(dst, val) xgene_set_bits(dst, val, 0, 3) +#define XG_RSIF_CONFIG1_REG_ADDR 0x00b8 +#define XG_RSIF_PLC_CLE_BUFF_THRESH 0x1 +#define RSIF_PLC_CLE_BUFF_THRESH_SET(dst, val) xgene_set_bits(dst, val, 0, 2) #define XCLE_BYPASS_REG0_ADDR 0x0160 #define XCLE_BYPASS_REG1_ADDR 0x0164 #define XG_CFG_BYPASS_ADDR 0x0204