From patchwork Tue Nov 15 14:29:13 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 695044 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3tJ8tF1fFKz9t0q for ; Wed, 16 Nov 2016 01:29:57 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=baylibre-com.20150623.gappssmtp.com header.i=@baylibre-com.20150623.gappssmtp.com header.b="d705zGpd"; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753295AbcKOO3p (ORCPT ); Tue, 15 Nov 2016 09:29:45 -0500 Received: from mail-wm0-f49.google.com ([74.125.82.49]:35166 "EHLO mail-wm0-f49.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S938635AbcKOO3k (ORCPT ); Tue, 15 Nov 2016 09:29:40 -0500 Received: by mail-wm0-f49.google.com with SMTP id a197so170491653wmd.0 for ; Tue, 15 Nov 2016 06:29:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=T4id9FddTXFmZ5BEY+LOw40LlTaQHTo4yD5PbgVEbN4=; b=d705zGpd9c6TgpUKH8B9xl+GMbfm/4X6ClSHsVAHpyrp5DeJShHJ5MRiz9DKDC0IDD OzcMrRkwm0Y2FO1Yk7NAsRLgiFwuliku+ZE92aB4on1vtcZQzCy5B8FjXQ8m0HUXkEoM J1xd73dyof5SsIDhZ3oIK6DgC2cTFPAtCLHyTegqpXvQc8kfDblDIDoiKjBvGrzBLmyc GvXvEAygY8KuHbWmoIjgmphyXmzMnHRSp1c91T7tSqA8jYI0tPQTQ0grWx3vTrrLP6Py EgWMeJMVi+Ak8IB3kYnsbvCMbOwD20yL7S+xO23mzuYNQjLako0qoOvQ6XbuLIj9UB4o 328w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=T4id9FddTXFmZ5BEY+LOw40LlTaQHTo4yD5PbgVEbN4=; b=Yyh9uA8JJ/upoJAezsgvGcx8dkwH9WLLbJUI5KuX0V4sp5kuFOaY+LF1Kvfh8nk9/f U7ZynIE8QJWIJ8sv+eWxYRbYApC4T4qCsUP1iPQCtmvZM+UQY/o0inulb6SQVdJeaqDr C/GjnYr98g5osqn5AOA/d4PnP0IbBpdkx4qrSdmlw6kLQ3lJ9Q9evt9UL43UEPgTI4Os /ED6AW54DbSHf80S7KHA5zbbf7nxFpaa7QcHd1zn57ICrN0TzVgAv6G0u88tvGGPIYQh E7NlImpRdCNEjXbuh/AO2KxlxQkMwFmukhffNovR0NqPt7C7E3V+A0siXap+f6yiOFZS LzSw== X-Gm-Message-State: ABUngvermgYYg+DAPcMS3o1/HyI0SxYwQ+bDg+DB2MDThGjtoKa78KvSOQcl5R/IsLP9VhGp X-Received: by 10.28.6.203 with SMTP id 194mr3906993wmg.16.1479220178568; Tue, 15 Nov 2016 06:29:38 -0800 (PST) Received: from boomer.baylibre.com ([90.63.244.31]) by smtp.googlemail.com with ESMTPSA id kp5sm7619219wjb.8.2016.11.15.06.29.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 15 Nov 2016 06:29:38 -0800 (PST) From: Jerome Brunet To: netdev@vger.kernel.org, devicetree@vger.kernel.org, Florian Fainelli Cc: Jerome Brunet , Carlo Caione , Kevin Hilman , Giuseppe Cavallaro , Alexandre TORGUE , Martin Blumenstingl , Andre Roth , Neil Armstrong , linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH net 2/3] dt-bindings: net: add DT bindings for realtek phys Date: Tue, 15 Nov 2016 15:29:13 +0100 Message-Id: <1479220154-25851-3-git-send-email-jbrunet@baylibre.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1479220154-25851-1-git-send-email-jbrunet@baylibre.com> References: <1479220154-25851-1-git-send-email-jbrunet@baylibre.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Signed-off-by: Jerome Brunet Signed-off-by: Neil Armstrong --- .../devicetree/bindings/net/realtek-phy.txt | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/realtek-phy.txt diff --git a/Documentation/devicetree/bindings/net/realtek-phy.txt b/Documentation/devicetree/bindings/net/realtek-phy.txt new file mode 100644 index 000000000000..dc2845a6b387 --- /dev/null +++ b/Documentation/devicetree/bindings/net/realtek-phy.txt @@ -0,0 +1,20 @@ +Realtek Ethernet PHY + +Some boards require special tuning values of the phy. + +Optional properties: + +realtek,disable-eee-1000t: +realtek,disable-eee-100tx: + If set, respectively disable 1000-BaseT and 100-BaseTx energy efficient + ethernet capabilty advertisement + default: Leave the phy default settings unchanged (capabilities advertised) + +Example: + +&mdio0 { + ethernetphy0: ethernet-phy@0 { + reg = <0>; + realtek,disable-eee-1000t; + }; +};