From patchwork Mon Oct 31 23:00:27 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Iyappan Subramanian X-Patchwork-Id: 689695 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3t78wB4b7yz9srZ for ; Tue, 1 Nov 2016 10:00:26 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=apm.com header.i=@apm.com header.b=CIJl+Byn; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S947903AbcJaXAW (ORCPT ); Mon, 31 Oct 2016 19:00:22 -0400 Received: from mail-oi0-f51.google.com ([209.85.218.51]:32824 "EHLO mail-oi0-f51.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S947895AbcJaXAU (ORCPT ); Mon, 31 Oct 2016 19:00:20 -0400 Received: by mail-oi0-f51.google.com with SMTP id 128so59561873oih.0 for ; Mon, 31 Oct 2016 16:00:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=apm.com; s=apm; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=i8pPC5uJRn2NuqhlKM3KCYEBWaopVZI6A2G4AfL8g0s=; b=CIJl+Bynh2b2sJT/8at2tjKKHDegu809ioaMHcoXT2x9LHPd0CGJXp5b8B5PkT8No4 WPdgyGxvjWWSTLg5dAu2pNz87IfsMRwetdD+Gv764r8soBrVoI908M5XMf4U4RupqJUi zzAuM6777JdYvuEfvEAVavMoIZDvsGHZCbx/M= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=i8pPC5uJRn2NuqhlKM3KCYEBWaopVZI6A2G4AfL8g0s=; b=MtdmGONXbckT5cpWya8z5rLa8tpPQilf8+LsOtyPMfc2zSld5kmqDB3sTpe9V5ckr+ 5j9979KFaiPvPOZcx9hq0ZDuwJC6jeGBk+HOZIdNzSlcROgVOOpEs55YOlQEJ42fNdiE Iy5SBC3pbL3/fR4sTRJvxRUHFSQlPNYf8vXM8Yv7/xyAMyVOkREpDn8XSuOVouOAeEsw GV4ZZNxG+2AOUQfeYZ3wiNpFDXHTYFtNZiGFhL4pMexNG7+Af0WdbSAciB2LeBN0/19l 9afRln5YWsY7PvoNIms38wB/dafol5QADUMOZ2+AzNAoAapXLRkeN+qRNIaHG+anxyeJ Zj3w== X-Gm-Message-State: ABUngvdxSAUBhMoevg60nvwgEXmPdDI4VytJTz6WLoMCa4Hzwue9UGPJ2MMQ8cqHEf7bRVhI X-Received: by 10.36.106.76 with SMTP id l73mr9437855itc.115.1477954819494; Mon, 31 Oct 2016 16:00:19 -0700 (PDT) Received: from isubrama-dev.amcc.com ([206.80.4.98]) by smtp.gmail.com with ESMTPSA id h137sm9333680itb.17.2016.10.31.16.00.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 31 Oct 2016 16:00:19 -0700 (PDT) From: Iyappan Subramanian To: davem@davemloft.net, netdev@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, patches@apm.com, Iyappan Subramanian , Toan Le Subject: [PATCH net-next 2/2] drivers: net: xgene: fix: Coalescing values for v2 hardware Date: Mon, 31 Oct 2016 16:00:27 -0700 Message-Id: <1477954827-9951-3-git-send-email-isubramanian@apm.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1477954827-9951-1-git-send-email-isubramanian@apm.com> References: <1477954827-9951-1-git-send-email-isubramanian@apm.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Changing the interrupt trigger region id to 2 and the corresponding threshold set0/set1 values to 8/16. Signed-off-by: Iyappan Subramanian Signed-off-by: Toan Le --- drivers/net/ethernet/apm/xgene/xgene_enet_hw.h | 2 ++ drivers/net/ethernet/apm/xgene/xgene_enet_ring2.c | 12 +++++++----- 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/apm/xgene/xgene_enet_hw.h b/drivers/net/ethernet/apm/xgene/xgene_enet_hw.h index 8456337..06e598c 100644 --- a/drivers/net/ethernet/apm/xgene/xgene_enet_hw.h +++ b/drivers/net/ethernet/apm/xgene/xgene_enet_hw.h @@ -55,8 +55,10 @@ enum xgene_enet_rm { #define PREFETCH_BUF_EN BIT(21) #define CSR_RING_ID_BUF 0x000c #define CSR_PBM_COAL 0x0014 +#define CSR_PBM_CTICK0 0x0018 #define CSR_PBM_CTICK1 0x001c #define CSR_PBM_CTICK2 0x0020 +#define CSR_PBM_CTICK3 0x0024 #define CSR_THRESHOLD0_SET1 0x0030 #define CSR_THRESHOLD1_SET1 0x0034 #define CSR_RING_NE_INT_MODE 0x017c diff --git a/drivers/net/ethernet/apm/xgene/xgene_enet_ring2.c b/drivers/net/ethernet/apm/xgene/xgene_enet_ring2.c index 2b76732..af51dd5 100644 --- a/drivers/net/ethernet/apm/xgene/xgene_enet_ring2.c +++ b/drivers/net/ethernet/apm/xgene/xgene_enet_ring2.c @@ -30,7 +30,7 @@ static void xgene_enet_ring_init(struct xgene_enet_desc_ring *ring) ring_cfg[0] |= SET_VAL(X2_INTLINE, ring->id & RING_BUFNUM_MASK); ring_cfg[3] |= SET_BIT(X2_DEQINTEN); } - ring_cfg[0] |= SET_VAL(X2_CFGCRID, 1); + ring_cfg[0] |= SET_VAL(X2_CFGCRID, 2); addr >>= 8; ring_cfg[2] |= QCOHERENT | SET_VAL(RINGADDRL, addr); @@ -192,13 +192,15 @@ static u32 xgene_enet_ring_len(struct xgene_enet_desc_ring *ring) static void xgene_enet_setup_coalescing(struct xgene_enet_desc_ring *ring) { - u32 data = 0x7777; + u32 data = 0x77777777; xgene_enet_ring_wr32(ring, CSR_PBM_COAL, 0x8e); + xgene_enet_ring_wr32(ring, CSR_PBM_CTICK0, data); xgene_enet_ring_wr32(ring, CSR_PBM_CTICK1, data); - xgene_enet_ring_wr32(ring, CSR_PBM_CTICK2, data << 16); - xgene_enet_ring_wr32(ring, CSR_THRESHOLD0_SET1, 0x40); - xgene_enet_ring_wr32(ring, CSR_THRESHOLD1_SET1, 0x80); + xgene_enet_ring_wr32(ring, CSR_PBM_CTICK2, data); + xgene_enet_ring_wr32(ring, CSR_PBM_CTICK3, data); + xgene_enet_ring_wr32(ring, CSR_THRESHOLD0_SET1, 0x08); + xgene_enet_ring_wr32(ring, CSR_THRESHOLD1_SET1, 0x10); } struct xgene_ring_ops xgene_ring2_ops = {