From patchwork Fri Oct 21 14:40:31 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 685160 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3t0pMQ5mMhz9t1Y for ; Sat, 22 Oct 2016 01:43:30 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=baylibre-com.20150623.gappssmtp.com header.i=@baylibre-com.20150623.gappssmtp.com header.b=JZWb5INi; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934786AbcJUOnZ (ORCPT ); Fri, 21 Oct 2016 10:43:25 -0400 Received: from mail-qt0-f182.google.com ([209.85.216.182]:33466 "EHLO mail-qt0-f182.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934417AbcJUOk5 (ORCPT ); Fri, 21 Oct 2016 10:40:57 -0400 Received: by mail-qt0-f182.google.com with SMTP id s49so89034842qta.0 for ; Fri, 21 Oct 2016 07:40:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=lVrcS71+o3sVJNF5QPt39pGDDQ7RK/0c4BiVbj8zi0I=; b=JZWb5INiZf/ArCNoXeLLj8keGxOBzcnKdqrdb+VoIHPcZb5Y4Ehcg10VCzrDrBbr+d b19/vg6Ym4qOTtbRj2kFP2IN6Q10qbxF0xkYBoZcse767xJusFatHVyXQdHkvU3PHXPd QQxa4SWgLGS0QsdVDkduIU1Z1wayV3TtmMW5yZHVDf/59z4eGTDcJzfLqYRLIhXk7D0R qQbWHuvD5l8hY0aIUBoMPNfPj44c7GSmFw5FHb5PcDdafu9uxp1K4guwDhOhxUPSBGyT gaFEUYb2BP3KUydKgzk/lIM+YAlJudVadSQrQR0AZp7kzBY7e6EXv2cww/n9iZI6AqUq STdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=lVrcS71+o3sVJNF5QPt39pGDDQ7RK/0c4BiVbj8zi0I=; b=GZruyana2P15G4BC83A5WARFQtoAp07x9cnfa44IljE0t7HyjsWuq8H0gQ1BpywC2t 6SbFW9yH1u1OVZrUXj5eLIVuYaFxtxRaUpUo30ZEjSpeAbmhonI3pdZZU56CKFO0U7s3 cuH9vyxToVL16izS4Fk+w0U04QVu9o5bt1Bisfp3Xauiqh8BNSWmPs059RwYSoN+fM81 cCt0hv2Ip9fhEp+wyqyaPpIWcFNWxhi2+OsXEZwUFluzsFp4M3QjRRMmtCb4hp1VLP3G 4iUmuIELagfA6CTB4Z5IefOxyrWOWv83ZoLlhIb+eonqstEj8MqVI5SnvPKRFo2yrtkI haig== X-Gm-Message-State: AA6/9Rn1BYOAWj4fY8Ll6vhzFdUY61Uorv1XzekvGvKd4X13tOSemtS8aKmDsUAY09AwZcXQ X-Received: by 10.28.223.84 with SMTP id w81mr3229100wmg.98.1477060855119; Fri, 21 Oct 2016 07:40:55 -0700 (PDT) Received: from localhost.localdomain (LFbn-1-1885-126.w90-73.abo.wanadoo.fr. [90.73.182.126]) by smtp.gmail.com with ESMTPSA id jt8sm3223281wjc.33.2016.10.21.07.40.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 21 Oct 2016 07:40:54 -0700 (PDT) From: Neil Armstrong To: khilman@baylibre.com, carlo@caione.org, linus.walleij@linaro.org Cc: Neil Armstrong , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org Subject: [RFC PATCH 06/13] ARM64: dts: meson-gxl: Add MMC/SD/SDIO nodes Date: Fri, 21 Oct 2016 16:40:31 +0200 Message-Id: <1477060838-14164-7-git-send-email-narmstrong@baylibre.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1477060838-14164-1-git-send-email-narmstrong@baylibre.com> References: <1477060838-14164-1-git-send-email-narmstrong@baylibre.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Add MMC/SD/SDIO nodes clock attributes for Amlogic Meson GXL. Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi index b45df2a..d1bf381 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi @@ -235,3 +235,24 @@ &i2c_C { clocks = <&clkc CLKID_I2C>; }; + +&sd_emmc_a { + clocks = <&clkc CLKID_SD_EMMC_A>, + <&xtal>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; +}; + +&sd_emmc_b { + clocks = <&clkc CLKID_SD_EMMC_B>, + <&xtal>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; +}; + +&sd_emmc_c { + clocks = <&clkc CLKID_SD_EMMC_C>, + <&xtal>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; +};