From patchwork Thu Sep 15 14:26:39 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Crispin X-Patchwork-Id: 670441 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3sZgmg1pPWz9sRZ for ; Fri, 16 Sep 2016 00:30:11 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933142AbcIOO1z (ORCPT ); Thu, 15 Sep 2016 10:27:55 -0400 Received: from nbd.name ([46.4.11.11]:50603 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758554AbcIOO05 (ORCPT ); Thu, 15 Sep 2016 10:26:57 -0400 From: John Crispin To: "David S. Miller" , Andrew Lunn , Florian Fainelli Cc: linux-kernel@vger.kernel.org, netdev@vger.kernel.org, qsdk-review@qca.qualcomm.com, John Crispin , devicetree@vger.kernel.org Subject: [PATCH V3 1/3] Documentation: devicetree: add qca8k binding Date: Thu, 15 Sep 2016 16:26:39 +0200 Message-Id: <1473949601-20674-2-git-send-email-john@phrozen.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1473949601-20674-1-git-send-email-john@phrozen.org> References: <1473949601-20674-1-git-send-email-john@phrozen.org> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Add device-tree binding for ar8xxx switch families. Cc: devicetree@vger.kernel.org Signed-off-by: John Crispin Reviewed-by: Andrew Lunn Reviewed-by: Florian Fainelli --- Changes in V2 * fixup example to include phy nodes and corresponding phandles * add a note explaining why we need to phy nodes Changes in V3 * add note stating that the cpu port is always 0 .../devicetree/bindings/net/dsa/qca8k.txt | 89 ++++++++++++++++++++ 1 file changed, 89 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/dsa/qca8k.txt diff --git a/Documentation/devicetree/bindings/net/dsa/qca8k.txt b/Documentation/devicetree/bindings/net/dsa/qca8k.txt new file mode 100644 index 0000000..9c67ee4 --- /dev/null +++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt @@ -0,0 +1,89 @@ +* Qualcomm Atheros QCA8xxx switch family + +Required properties: + +- compatible: should be "qca,qca8337" +- #size-cells: must be 0 +- #address-cells: must be 1 + +Subnodes: + +The integrated switch subnode should be specified according to the binding +described in dsa/dsa.txt. As the QCA8K switches do not have a N:N mapping of +port and PHY id, each subnode describing a port needs to have a valid phandle +referencing the internal PHY connected to it. The CPU port of this switch is +always port 0. + +Example: + + + &mdio0 { + phy_port1: phy@0 { + reg = <0>; + }; + + phy_port2: phy@1 { + reg = <1>; + }; + + phy_port3: phy@2 { + reg = <2>; + }; + + phy_port4: phy@3 { + reg = <3>; + }; + + phy_port5: phy@4 { + reg = <4>; + }; + + switch0@0 { + compatible = "qca,qca8337"; + #address-cells = <1>; + #size-cells = <0>; + + reg = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + label = "cpu"; + ethernet = <&gmac1>; + phy-mode = "rgmii"; + }; + + port@1 { + reg = <1>; + label = "lan1"; + phy-handle = <&phy_port1>; + }; + + port@2 { + reg = <2>; + label = "lan2"; + phy-handle = <&phy_port2>; + }; + + port@3 { + reg = <3>; + label = "lan3"; + phy-handle = <&phy_port3>; + }; + + port@4 { + reg = <4>; + label = "lan4"; + phy-handle = <&phy_port4>; + }; + + port@5 { + reg = <5>; + label = "wan"; + phy-handle = <&phy_port5>; + }; + }; + }; + };