From patchwork Mon Jun 6 06:30:01 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiang Zhao X-Patchwork-Id: 630646 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3rNQ8B55PVz9t2p for ; Mon, 6 Jun 2016 16:41:14 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751651AbcFFGkx (ORCPT ); Mon, 6 Jun 2016 02:40:53 -0400 Received: from mail-by2on0083.outbound.protection.outlook.com ([207.46.100.83]:25376 "EHLO na01-by2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751579AbcFFGku (ORCPT ); Mon, 6 Jun 2016 02:40:50 -0400 Received: from DM2PR03CA0028.namprd03.prod.outlook.com (10.141.96.27) by BY2PR0301MB0709.namprd03.prod.outlook.com (10.160.63.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id 15.1.506.9; Mon, 6 Jun 2016 06:40:37 +0000 Received: from BN1BFFO11FD034.protection.gbl (2a01:111:f400:7c10::1:105) by DM2PR03CA0028.outlook.office365.com (2a01:111:e400:2428::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id 15.1.511.8 via Frontend Transport; Mon, 6 Jun 2016 06:40:37 +0000 Authentication-Results: spf=fail (sender IP is 192.88.168.50) smtp.mailfrom=nxp.com; nxp.com; dkim=none (message not signed) header.d=none; nxp.com; dmarc=none action=none header.from=nxp.com; nxp.com; dkim=none (message not signed) header.d=none; Received-SPF: Fail (protection.outlook.com: domain of nxp.com does not designate 192.88.168.50 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.168.50; helo=tx30smr01.am.freescale.net; Received: from tx30smr01.am.freescale.net (192.88.168.50) by BN1BFFO11FD034.mail.protection.outlook.com (10.58.144.97) with Microsoft SMTP Server (TLS) id 15.1.497.8 via Frontend Transport; Mon, 6 Jun 2016 06:40:37 +0000 Received: from titan.ap.freescale.net ([10.192.208.233]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id u566eCUw024075; Sun, 5 Jun 2016 23:40:34 -0700 From: Zhao Qiang To: , , CC: , , , , Zhao Qiang Subject: [Patch v3 4/5] fsl/qe: Add QE TDM lib Date: Mon, 6 Jun 2016 14:30:01 +0800 Message-ID: <1465194602-43209-4-git-send-email-qiang.zhao@nxp.com> X-Mailer: git-send-email 2.1.0.27.g96db324 In-Reply-To: <1465194602-43209-1-git-send-email-qiang.zhao@nxp.com> References: <1465194602-43209-1-git-send-email-qiang.zhao@nxp.com> X-EOPAttributedMessage: 0 X-Matching-Connectors: 131096688373161034; (91ab9b29-cfa4-454e-5278-08d120cd25b8); () X-Forefront-Antispam-Report: CIP:192.88.168.50; IPV:NLI; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(979002)(6009001)(2980300002)(1109001)(1110001)(339900001)(199003)(50944005)(189002)(9170700003)(47776003)(5008740100001)(104016004)(87936001)(2950100001)(6806005)(77096005)(19580395003)(105606002)(19580405001)(36756003)(106466001)(50226002)(85426001)(8936002)(2906002)(4326007)(8666004)(575784001)(48376002)(5001770100001)(86362001)(92566002)(50986999)(33646002)(76176999)(586003)(11100500001)(50466002)(8676002)(5003940100001)(229853001)(189998001)(81166006)(2201001)(7059030)(2004002)(969003)(989001)(999001)(1009001)(1019001); DIR:OUT; SFP:1101; SCL:1; SRVR:BY2PR0301MB0709; H:tx30smr01.am.freescale.net; FPR:; SPF:Fail; MLV:ovrnspm; A:1; MX:1; PTR:InfoDomainNonexistent; LANG:en; X-Microsoft-Exchange-Diagnostics: 1; BN1BFFO11FD034; 1:itAFOtmPw2hENvqRTsFO0OLcq2MMclgb/580Vut/KXXjx2qZDrbJ9HW1grX4k1vxqaqB6z2ZkgBPqDozYkIzhXx1pHz0OvfyeUx4Y//OtDhoUq6o1qRwt0TJmBVpZJHbPYhyZeNrP3cSJbZN9Zw31KRL3y6i1KaI/tMEOehXixkj6cJBBExwucEHbjD/enOoY9vPk0wYU4DkbSYf6MkjXUQsQb7QmLggR2+Llzuz3Y6M8Zg94TrkH7llLbtb54Z8sRD8DNKl5yG4GHgzvE1+aWowVxtmNVBjfJn3/w2FUWjgdc4fvH6HeGYj5fJ6NBYrO8Bbr+xEqDPmhD2Hun6gq5+iwpCyj18xhOTwlTKOd6xQBTDR7pZ9dHtOO1aH9dGkQdeMd4+ZP467BE0JmhkivbtFHFcACGLs90YAYAqb2XfWq+BWp7LMWHpRCOMVAhAVmUmPvyOu4B7NJxa6JAI/UEADJ2Fr74WHabRaNB7YmzJayAzP3RwhCuseM0exLvOaE/bf0XEv4aDg2fmfo4JupdKL5FTQev6JXv3j7owytj+vA14OmS24ZjVhkKK6Xa3HsuzMGsOJba2YcJJpQcGulzlVS3u/oFPIkgsMnBM8MIbjJxjYGPaorXuxEMKNKGl7dmJSBNRj0wfob74025LdQ8hk0ZL4GQkCUAAdSS1sAZtKHa3W2ZU3O9EqRvRGDHtY MIME-Version: 1.0 X-MS-Office365-Filtering-Correlation-Id: 279a7247-a287-406e-9988-08d38dd57828 X-Microsoft-Exchange-Diagnostics: 1; BY2PR0301MB0709; 2:/fHhIKfsEMXOXVHfwN/tTB+XuaR0NqETtsz5qLSlo3CJfDmemg2zGUOCja8pmVzqu1sCZNbhco+s5uUOZpJk4kcJMwOXGrYxBfWOaWTjwCkPdL2iH9OiW21dKq7AyZDikJh713hXwEvxKHiHZ87dUh79aIUFId+LdIflGVxsubBH78n2cuTphrosOUixWMfg; 3:C7x2xyrzBPkik1QBcm2ExkZsHikHzcxurVVZy465p6cxle/5yoSaO5HDPSZMbrCeHLbcdkaQ71K7CGEDPsSTD0zs8azgUgxvSVv3LLaHFbMuX5RepxYJAffnQhjcY5XLfsZ1hYrzAKVxRvUEKlIftVot/ralLsgtN7Usoq44MmfgG0Gqhpxt9lL1JHZtQImkELGWgW1USlhgAdNVCiRCuz1OkclPM9cpxLRSwJxF7C8= X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BY2PR0301MB0709; X-Microsoft-Exchange-Diagnostics: 1; BY2PR0301MB0709; 25:D0K21OpNeRP6XpoBkXE9SCX8zWR6OiXPQr9ixylZWM8nWIIOmkM8FVBZAkI3PQWKs9+A7nffjMBRvzcj3rs6boJngl1p56i80Ar5ygAvX9+cHREA5/izQgHp5S3gwJtEIQ0JRpIwEjqkDwSoY6S1/S6dmsTHd/NcchkxZDnI2jCUMRsY8Vc2Vyexzg4AEfivOE7TzjCtWYbhFdKi+STBs2IXEI2uS88Nm0M0A341vaaVUMI1F9mz7fBKCtmwwS4YSE7C1dKYT3uPOHxb7QjmBtDTikBo5fn6CiZqUEms+O+hFYAGSU/QB5kjCzMWm8DdrISJk9cAihN8rOvpJCh1IGP2a7T6Z0G6TN62CarfTa3cLULVCWOILDoNywSvWLWd6LUdjT8+b1UOP5chwCOrhsD9wGGiSfSminDF9SQoOxG/0zCv+kFWC3+83pAQhfrT7Vf8f3C7XMqIQ/WYdMWPaUA68vtKEIbY30MyOyc9On23QnhSCnsz5uCs88hkgTqcJtLCdH6TEJ4zrbuu1+Z/cDyn6nAC5yrnnnvub86r0/awNIF4Ft2rC6gv+zQxl9okWozFXTMHBdhDHgm3i5sUCDYnYAjJsqIJiQcKLFvK9PwSvUT8harUddSeway96ysN4AB9nRxaxJwXe4NiX1APSsPJRQdPEFd39eH6KS06Ib5XgJ+1AhLgxhgdQATCT90UteuxXzmjkjEY/Njt92sCiw== X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:(185117386973197); X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(601004)(2401047)(5005006)(13024025)(8121501046)(13015025)(13017025)(13018025)(13023025)(3002001)(10201501046)(6055026); SRVR:BY2PR0301MB0709; BCL:0; PCL:0; RULEID:(400006); SRVR:BY2PR0301MB0709; X-Microsoft-Exchange-Diagnostics: 1; BY2PR0301MB0709; 4:IWbpWz5MkPR7+JKTQKIKmnl4T++ajrODAuSdt57+Rth7C2LIFvPsnCy6PUKrM4ij1ix5ZM1S5c9gLQb5jOMe4kV+iXEgVap8JG0OeY2TLI+KlnNInNjUzDZ5c8mqryb9StOF/3PV4S7o8nj3WF/fpzLXvUTnjmmnssC+B2xpAfSf4DRAq28sCUb0/HunlFPlxiih45kiRk1OJbtDbMW/0IeNm17EIt/giTkb74w3SB7Dgafh2ACl/oNJnadss72q1jE2ql+hTNErLejYPGcivn7Ir/HEmXDH528XCr5dst0y8es+cgKuThBHr6Cc+t7Hhe30r8Bi1KsSWHH470mdIftm9842Tt0D8mzLD68qDuHKYfApxluOcIBNugyrTwgjNTAROkB7i8kPhR1IUfGyR6d0+9pK3xMR4dvwbgZw9V95Lk75ak0Y3NQOJjTxjnhgMXlQXxPhSS1CLQoK+2TU1nfDsTGoAR/AqztqtLf6tiIf5Tp3hasn0h8/K3Y5V8bJNYjfga+mcvIhk8GHP25Tog== X-Forefront-PRVS: 096507C068 X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; BY2PR0301MB0709; 23:91qGOcMEMCO0zRKZo35JL0R555RvSIqIJcGsbm3?= =?us-ascii?Q?tTO+LRkhUdD9ttbH99+7/SJ6udSK68m/geEO3S5BPtBfqCnIklf3/cIlF60T?= =?us-ascii?Q?fh+JeBMNAMrHytOA7JuXiy8vq9c6BIBQENZsK1FyCHZnAujbWfF9EABkGSSh?= =?us-ascii?Q?dLNL8XgtGiECxzMakk0MCJ/+GnNaF2W6WbE52MrsmRQ4SkZL+zp/simRyE+w?= =?us-ascii?Q?KiH7ZX6jvLL4rt08Awgut/lW0GhErGzMoQezNe3gBxI8oTImcMA/B7JfcOTn?= =?us-ascii?Q?3a1hIOvWVyCcrYSYMnDy0H75znQTaMKYp+nHcKV03JHlMxazCnbqp4RHrTyR?= =?us-ascii?Q?7TWcAHumWLYCW1n6nxzxlzBwwQZCZNOPYzTXA3zLx4sRDotz2hnOR+2+3LWQ?= =?us-ascii?Q?4tk1CVQOoftx4/pdjBWTyPCfdAyjlCIzxM4WttqCjQ9POPQyrbUditXywMjN?= =?us-ascii?Q?ucB4kM4z5MPGS3PcQY7CS5YgmzcdLWXNIOd06O3VdY3t9kn9VpkPmIZcvYUA?= =?us-ascii?Q?jjQpzxUOlVGypUFNX7DXGuVJlKVYptt5bKY50UZ5a0t6z7ocO9qVwem+cW81?= =?us-ascii?Q?ZL72sPAErNwkPPX5ZKCjWxjVnkJaiAixncTJkk4SYB/F479f+CwhbxvpXvBE?= =?us-ascii?Q?6wiFqqzjgMNyrBzttfDoLjp9nSaEw6LOCTEru8zBl1GYk9mSwbQarExOeES2?= =?us-ascii?Q?6CZXNTw8KfCVWZOjLtGH9ggBxeG0GhSFe71Q/blaErPj75h1C/DcdjonW54v?= =?us-ascii?Q?y3qOQzTF55akDPoMGsA0yA06TnZvIx9PSLPRIdrL7d3Vt/HL4oCrgXcDmiIi?= =?us-ascii?Q?w2/lrzSeNIjnCRaZRIJloo0sFHTXPBRwHGPUbaMx/gez1Fzt6CrJPxuc5s/s?= =?us-ascii?Q?MbPD0Tbm5yIaDNJdPEBjTyUihVMgxj8ooLAQ6bpiPMJiUiqW/AwI5z5X2mS2?= =?us-ascii?Q?T4zay4iXe/kVgX1y2A4BzT9qDnB9d0WUpjek15LPrGIIr/JHiFPSYMf1lzkt?= =?us-ascii?Q?BQguL0kDoEwHCv2+GX3pMhLv6Dv6xv3siZJ5RkRv4LsVw9UHvsvzJpkU+x5r?= =?us-ascii?Q?F12FDika75gGwUtNgtjnShsaj0mb5aL0JmxnF64s1EWZLV6+j781a/RuMzlB?= =?us-ascii?Q?Yuyo39hVbu8KW7XESCZdcS1QcnLwV2yrD+SeJKQGZda4dgxaE+B3FgItuLns?= =?us-ascii?Q?+JcElbDHZKF1U93IQKopaEtPhKHZGuELz5tjJjltIIkhLEBJrs5bCjwOP3Xi?= =?us-ascii?Q?JbwvTWKuKyWrBiuagRYl76oNBd6rTvSiRfO+aLZ5n?= X-Microsoft-Exchange-Diagnostics: 1; BY2PR0301MB0709; 5:pRIddDs3ZJjThu1S60hfxHkfQUnB1NnopfG9ZUkIosJpHzBfzMR7cpQNWLmiNCfOKX2LFwfDmYjOwhEQzbEM5arrLj9F9dEYJXQ1/g9Z+hum0Jt+ayrT7svZqn+B9VSb33eu70tlq2SSf/w5Yh0WorBgFGJvIyL5OOM4ghQMz0Y=; 24:A084i5E2FNF7iq0CzioMyx2HIHP76q0rKoHjPQCo0tkE+gbCZ+qlUFMqKV2VFS1ge/ZT8E5rHGA7uuV66CKdNFTSR4/9wYSGZr9gtDXnWKk=; 7:OUxOMSs8AmDlr8W/aFK6Cy2BGCOiBZqu47uJGyYCwxQosjg35vA9b4NdZVQeB+RTW2llOrOSSK3pIoLytrBpIkN3mcbEZg2f8klp7g61vUtT2OrjSPemCVvB+10sfl3SdSzBk8R8vo9cFM10FKI8IjM+G17Fa29pbQP1zKhw5RKmrbF+vJpgyNeOhT3alMv5fKmqDmweIDNB2EC1xHC0cJrz6TbhlOOVG7fkr0C/wRc= SpamDiagnosticOutput: 1:23 SpamDiagnosticMetadata: NSPM X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jun 2016 06:40:37.1133 (UTC) X-MS-Exchange-CrossTenant-Id: 5afe0b00-7697-4969-b663-5eab37d5f47e X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e; Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY2PR0301MB0709 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org QE has module to support TDM, some other protocols supported by QE are based on TDM. add a qe-tdm lib, this lib provides functions to the protocols using TDM to configurate QE-TDM. Signed-off-by: Zhao Qiang --- Changes for v2: - delete dead code - use strcmp instead of strcasecmp - use of_find_compatible_node instead of of_find_by_name - use devm_ioremap_resource - rename init_si to ucc_tdm_init - rename of_parse_tdm to ucc_of_parse_tdm - return err when there is not t1 or e1 Changes for v3: - na drivers/soc/fsl/qe/Kconfig | 6 +- drivers/soc/fsl/qe/Makefile | 1 + drivers/soc/fsl/qe/qe_tdm.c | 276 ++++++++++++++++++++++++++++++++++++++++++ include/soc/fsl/qe/immap_qe.h | 5 +- include/soc/fsl/qe/qe_tdm.h | 94 ++++++++++++++ 5 files changed, 377 insertions(+), 5 deletions(-) create mode 100644 drivers/soc/fsl/qe/qe_tdm.c create mode 100644 include/soc/fsl/qe/qe_tdm.h diff --git a/drivers/soc/fsl/qe/Kconfig b/drivers/soc/fsl/qe/Kconfig index 20978f2..73a2e08 100644 --- a/drivers/soc/fsl/qe/Kconfig +++ b/drivers/soc/fsl/qe/Kconfig @@ -22,7 +22,7 @@ config UCC_SLOW config UCC_FAST bool - default y if UCC_GETH + default y if UCC_GETH || QE_TDM help This option provides qe_lib support to UCC fast protocols: HDLC, Ethernet, ATM, transparent @@ -31,6 +31,10 @@ config UCC bool default y if UCC_FAST || UCC_SLOW +config QE_TDM + bool + default y if FSL_UCC_HDLC + config QE_USB bool default y if USB_FSL_QE diff --git a/drivers/soc/fsl/qe/Makefile b/drivers/soc/fsl/qe/Makefile index ffac541..2031d38 100644 --- a/drivers/soc/fsl/qe/Makefile +++ b/drivers/soc/fsl/qe/Makefile @@ -6,5 +6,6 @@ obj-$(CONFIG_CPM) += qe_common.o obj-$(CONFIG_UCC) += ucc.o obj-$(CONFIG_UCC_SLOW) += ucc_slow.o obj-$(CONFIG_UCC_FAST) += ucc_fast.o +obj-$(CONFIG_QE_TDM) += qe_tdm.o obj-$(CONFIG_QE_USB) += usb.o obj-$(CONFIG_QE_GPIO) += gpio.o diff --git a/drivers/soc/fsl/qe/qe_tdm.c b/drivers/soc/fsl/qe/qe_tdm.c new file mode 100644 index 0000000..5e48b14 --- /dev/null +++ b/drivers/soc/fsl/qe/qe_tdm.c @@ -0,0 +1,276 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. All rights reserved. + * + * Authors: Zhao Qiang + * + * Description: + * QE TDM API Set - TDM specific routines implementations. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include +#include +#include +#include +#include +#include + +static int set_tdm_framer(const char *tdm_framer_type) +{ + if (strcmp(tdm_framer_type, "e1") == 0) + return TDM_FRAMER_E1; + else if (strcmp(tdm_framer_type, "t1") == 0) + return TDM_FRAMER_T1; + else + return -EINVAL; +} + +static void set_si_param(struct ucc_tdm *utdm, struct ucc_tdm_info *ut_info) +{ + struct si_mode_info *si_info = &ut_info->si_info; + + if (utdm->tdm_mode == TDM_INTERNAL_LOOPBACK) { + si_info->simr_crt = 1; + si_info->simr_rfsd = 0; + } +} + +int ucc_of_parse_tdm(struct device_node *np, struct ucc_tdm *utdm, + struct ucc_tdm_info *ut_info) +{ + const char *sprop; + int ret = 0; + u32 val; + struct resource *res; + struct device_node *np2; + static int siram_init_flag; + struct platform_device *pdev; + + sprop = of_get_property(np, "fsl,rx-sync-clock", NULL); + if (sprop) { + ut_info->uf_info.rx_sync = qe_clock_source(sprop); + if ((ut_info->uf_info.rx_sync < QE_CLK_NONE) || + (ut_info->uf_info.rx_sync > QE_RSYNC_PIN)) { + pr_err("QE-TDM: Invalid rx-sync-clock property\n"); + return -EINVAL; + } + } else { + pr_err("QE-TDM: Invalid rx-sync-clock property\n"); + return -EINVAL; + } + + sprop = of_get_property(np, "fsl,tx-sync-clock", NULL); + if (sprop) { + ut_info->uf_info.tx_sync = qe_clock_source(sprop); + if ((ut_info->uf_info.tx_sync < QE_CLK_NONE) || + (ut_info->uf_info.tx_sync > QE_TSYNC_PIN)) { + pr_err("QE-TDM: Invalid tx-sync-clock property\n"); + return -EINVAL; + } + } else { + pr_err("QE-TDM: Invalid tx-sync-clock property\n"); + return -EINVAL; + } + + ret = of_property_read_u32_index(np, "fsl,tx-timeslot-mask", 0, &val); + if (ret) { + pr_err("QE-TDM: Invalid tx-timeslot-mask property\n"); + return -EINVAL; + } + utdm->tx_ts_mask = val; + + ret = of_property_read_u32_index(np, "fsl,rx-timeslot-mask", 0, &val); + if (ret) { + ret = -EINVAL; + pr_err("QE-TDM: Invalid rx-timeslot-mask property\n"); + return ret; + } + utdm->rx_ts_mask = val; + + ret = of_property_read_u32_index(np, "fsl,tdm-id", 0, &val); + if (ret) { + ret = -EINVAL; + pr_err("QE-TDM: No fsl,tdm-id property for this UCC\n"); + return ret; + } + utdm->tdm_port = val; + ut_info->uf_info.tdm_num = utdm->tdm_port; + + if (of_get_property(np, "fsl,tdm-internal-loopback", NULL)) + utdm->tdm_mode = TDM_INTERNAL_LOOPBACK; + else + utdm->tdm_mode = TDM_NORMAL; + + sprop = of_get_property(np, "fsl,tdm-framer-type", NULL); + if (!sprop) { + ret = -EINVAL; + pr_err("QE-TDM: No tdm-framer-type property for UCC\n"); + return ret; + } + ret = set_tdm_framer(sprop); + if (ret < 0) + return -EINVAL; + utdm->tdm_framer_type = ret; + + ret = of_property_read_u32_index(np, "fsl,siram-entry-id", 0, &val); + if (ret) { + ret = -EINVAL; + pr_err("QE-TDM: No siram entry id for UCC\n"); + return ret; + } + utdm->siram_entry_id = val; + + set_si_param(utdm, ut_info); + + np2 = of_find_compatible_node(NULL, NULL, "fsl,t1040-qe-si"); + if (!np2) + return -EINVAL; + + pdev = of_find_device_by_node(np2); + if (!pdev) { + pr_err("%s: failed to lookup pdev\n", np2->name); + of_node_put(np2); + return -EINVAL; + } + + of_node_put(np2); + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + utdm->si_regs = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(utdm->si_regs)) { + ret = PTR_ERR(utdm->si_regs); + goto err_miss_siram_property; + } + + np2 = of_find_compatible_node(NULL, NULL, "fsl,t1040-qe-siram"); + if (!np2) { + ret = -EINVAL; + goto err_miss_siram_property; + } + + pdev = of_find_device_by_node(np2); + if (!pdev) { + ret = -EINVAL; + pr_err("%s: failed to lookup pdev\n", np2->name); + of_node_put(np2); + goto err_miss_siram_property; + } + + of_node_put(np2); + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + utdm->siram = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(utdm->siram)) { + ret = PTR_ERR(utdm->siram); + goto err_miss_siram_property; + } + + if (siram_init_flag == 0) { + memset_io(utdm->siram, 0, res->end - res->start + 1); + siram_init_flag = 1; + } + + return ret; + +err_miss_siram_property: + devm_iounmap(&pdev->dev, utdm->si_regs); + return ret; +} + +void ucc_tdm_init(struct ucc_tdm *utdm, struct ucc_tdm_info *ut_info) +{ + struct si1 __iomem *si_regs; + u16 __iomem *siram; + u16 siram_entry_valid; + u16 siram_entry_closed; + u16 ucc_num; + u8 csel; + u16 sixmr; + u16 tdm_port; + u32 siram_entry_id; + u32 mask; + int i; + + si_regs = utdm->si_regs; + siram = utdm->siram; + ucc_num = ut_info->uf_info.ucc_num; + tdm_port = utdm->tdm_port; + siram_entry_id = utdm->siram_entry_id; + + if (utdm->tdm_framer_type == TDM_FRAMER_T1) + utdm->num_of_ts = 24; + if (utdm->tdm_framer_type == TDM_FRAMER_E1) + utdm->num_of_ts = 32; + + /* set siram table */ + csel = (ucc_num < 4) ? ucc_num + 9 : ucc_num - 3; + + siram_entry_valid = SIR_CSEL(csel) | SIR_BYTE | SIR_CNT(0); + siram_entry_closed = SIR_IDLE | SIR_BYTE | SIR_CNT(0); + + for (i = 0; i < utdm->num_of_ts; i++) { + mask = 0x01 << i; + + if (utdm->tx_ts_mask & mask) + iowrite16be(siram_entry_valid, + &siram[siram_entry_id * 32 + i]); + else + iowrite16be(siram_entry_closed, + &siram[siram_entry_id * 32 + i]); + + if (utdm->rx_ts_mask & mask) + iowrite16be(siram_entry_valid, + &siram[siram_entry_id * 32 + 0x200 + i]); + else + iowrite16be(siram_entry_closed, + &siram[siram_entry_id * 32 + 0x200 + i]); + } + + setbits16(&siram[(siram_entry_id * 32) + (utdm->num_of_ts - 1)], + SIR_LAST); + setbits16(&siram[(siram_entry_id * 32) + 0x200 + (utdm->num_of_ts - 1)], + SIR_LAST); + + /* Set SIxMR register */ + sixmr = SIMR_SAD(siram_entry_id); + + sixmr &= ~SIMR_SDM_MASK; + + if (utdm->tdm_mode == TDM_INTERNAL_LOOPBACK) + sixmr |= SIMR_SDM_INTERNAL_LOOPBACK; + else + sixmr |= SIMR_SDM_NORMAL; + + sixmr |= SIMR_RFSD(ut_info->si_info.simr_rfsd) | + SIMR_TFSD(ut_info->si_info.simr_tfsd); + + if (ut_info->si_info.simr_crt) + sixmr |= SIMR_CRT; + if (ut_info->si_info.simr_sl) + sixmr |= SIMR_SL; + if (ut_info->si_info.simr_ce) + sixmr |= SIMR_CE; + if (ut_info->si_info.simr_fe) + sixmr |= SIMR_FE; + if (ut_info->si_info.simr_gm) + sixmr |= SIMR_GM; + + switch (tdm_port) { + case 0: + iowrite16be(sixmr, &si_regs->sixmr1[0]); + break; + case 1: + iowrite16be(sixmr, &si_regs->sixmr1[1]); + break; + case 2: + iowrite16be(sixmr, &si_regs->sixmr1[2]); + break; + case 3: + iowrite16be(sixmr, &si_regs->sixmr1[3]); + break; + default: + pr_err("QE-TDM: can not find tdm sixmr reg\n"); + break; + } +} diff --git a/include/soc/fsl/qe/immap_qe.h b/include/soc/fsl/qe/immap_qe.h index bedbff8..c76ef30 100644 --- a/include/soc/fsl/qe/immap_qe.h +++ b/include/soc/fsl/qe/immap_qe.h @@ -159,10 +159,7 @@ struct spi { /* SI */ struct si1 { - __be16 siamr1; /* SI1 TDMA mode register */ - __be16 sibmr1; /* SI1 TDMB mode register */ - __be16 sicmr1; /* SI1 TDMC mode register */ - __be16 sidmr1; /* SI1 TDMD mode register */ + __be16 sixmr1[4]; /* SI1 TDMx (x = A B C D) mode register */ u8 siglmr1_h; /* SI1 global mode register high */ u8 res0[0x1]; u8 sicmdr1_h; /* SI1 command register high */ diff --git a/include/soc/fsl/qe/qe_tdm.h b/include/soc/fsl/qe/qe_tdm.h new file mode 100644 index 0000000..4c91498 --- /dev/null +++ b/include/soc/fsl/qe/qe_tdm.h @@ -0,0 +1,94 @@ +/* + * Internal header file for QE TDM mode routines. + * + * Copyright (C) 2016 Freescale Semiconductor, Inc. All rights reserved. + * + * Authors: Zhao Qiang + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version + */ + +#ifndef CONFIG_QE_TDM_H +#define CONFIG_QE_TDM_H + +#include +#include + +#include +#include + +#include +#include + +/* SI RAM entries */ +#define SIR_LAST 0x0001 +#define SIR_BYTE 0x0002 +#define SIR_CNT(x) ((x) << 2) +#define SIR_CSEL(x) ((x) << 5) +#define SIR_SGS 0x0200 +#define SIR_SWTR 0x4000 +#define SIR_MCC 0x8000 +#define SIR_IDLE 0 + +/* SIxMR fields */ +#define SIMR_SAD(x) ((x) << 12) +#define SIMR_SDM_NORMAL 0x0000 +#define SIMR_SDM_INTERNAL_LOOPBACK 0x0800 +#define SIMR_SDM_MASK 0x0c00 +#define SIMR_CRT 0x0040 +#define SIMR_SL 0x0020 +#define SIMR_CE 0x0010 +#define SIMR_FE 0x0008 +#define SIMR_GM 0x0004 +#define SIMR_TFSD(n) (n) +#define SIMR_RFSD(n) ((n) << 8) + +enum tdm_ts_t { + TDM_TX_TS, + TDM_RX_TS +}; + +enum tdm_framer_t { + TDM_FRAMER_T1, + TDM_FRAMER_E1 +}; + +enum tdm_mode_t { + TDM_INTERNAL_LOOPBACK, + TDM_NORMAL +}; + +struct si_mode_info { + u8 simr_rfsd; + u8 simr_tfsd; + u8 simr_crt; + u8 simr_sl; + u8 simr_ce; + u8 simr_fe; + u8 simr_gm; +}; + +struct ucc_tdm_info { + struct ucc_fast_info uf_info; + struct si_mode_info si_info; +}; + +struct ucc_tdm { + u16 tdm_port; /* port for this tdm:TDMA,TDMB */ + u32 siram_entry_id; + u16 __iomem *siram; + struct si1 __iomem *si_regs; + enum tdm_framer_t tdm_framer_type; + enum tdm_mode_t tdm_mode; + u8 num_of_ts; /* the number of timeslots in this tdm frame */ + u32 tx_ts_mask; /* tx time slot mask */ + u32 rx_ts_mask; /* rx time slot mask */ +}; + +int ucc_of_parse_tdm(struct device_node *np, struct ucc_tdm *utdm, + struct ucc_tdm_info *ut_info); +void ucc_tdm_init(struct ucc_tdm *utdm, struct ucc_tdm_info *ut_info); +#endif