From patchwork Mon Jun 6 06:29:59 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiang Zhao X-Patchwork-Id: 630645 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3rNQ8851wkz9t2p for ; Mon, 6 Jun 2016 16:41:12 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751458AbcFFGki (ORCPT ); Mon, 6 Jun 2016 02:40:38 -0400 Received: from mail-bl2on0089.outbound.protection.outlook.com ([65.55.169.89]:31076 "EHLO na01-bl2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1750929AbcFFGkg (ORCPT ); Mon, 6 Jun 2016 02:40:36 -0400 Received: from BN3PR0301CA0026.namprd03.prod.outlook.com (10.160.180.164) by BL2PR03MB1873.namprd03.prod.outlook.com (10.164.115.17) with Microsoft SMTP Server (TLS) id 15.1.427.16; Mon, 6 Jun 2016 06:40:27 +0000 Received: from BY2FFO11FD024.protection.gbl (2a01:111:f400:7c0c::134) by BN3PR0301CA0026.outlook.office365.com (2a01:111:e400:4000::36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id 15.1.506.9 via Frontend Transport; Mon, 6 Jun 2016 06:40:26 +0000 Authentication-Results: spf=fail (sender IP is 192.88.168.50) smtp.mailfrom=nxp.com; nxp.com; dkim=none (message not signed) header.d=none; nxp.com; dmarc=none action=none header.from=nxp.com; nxp.com; dkim=none (message not signed) header.d=none; Received-SPF: Fail (protection.outlook.com: domain of nxp.com does not designate 192.88.168.50 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.168.50; helo=tx30smr01.am.freescale.net; Received: from tx30smr01.am.freescale.net (192.88.168.50) by BY2FFO11FD024.mail.protection.outlook.com (10.1.15.213) with Microsoft SMTP Server (TLS) id 15.1.497.8 via Frontend Transport; Mon, 6 Jun 2016 06:40:25 +0000 Received: from titan.ap.freescale.net ([10.192.208.233]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id u566eCUu024075; Sun, 5 Jun 2016 23:40:22 -0700 From: Zhao Qiang To: , , CC: , , , , Zhao Qiang Subject: [Patch v3 2/5] fsl/qe: setup clock source for TDM mode Date: Mon, 6 Jun 2016 14:29:59 +0800 Message-ID: <1465194602-43209-2-git-send-email-qiang.zhao@nxp.com> X-Mailer: git-send-email 2.1.0.27.g96db324 In-Reply-To: <1465194602-43209-1-git-send-email-qiang.zhao@nxp.com> References: <1465194602-43209-1-git-send-email-qiang.zhao@nxp.com> X-EOPAttributedMessage: 0 X-Matching-Connectors: 131096688261227945; (91ab9b29-cfa4-454e-5278-08d120cd25b8); () X-Forefront-Antispam-Report: CIP:192.88.168.50; IPV:NLI; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(6009001)(2980300002)(1109001)(1110001)(339900001)(189002)(199003)(9170700003)(2950100001)(8666004)(8676002)(229853001)(4326007)(586003)(19580395003)(8936002)(77096005)(189998001)(33646002)(48376002)(76176999)(50986999)(87936001)(50226002)(2201001)(50466002)(92566002)(19580405001)(81166006)(85426001)(47776003)(5003940100001)(105606002)(104016004)(86362001)(2906002)(6806005)(5001770100001)(5008740100001)(106466001)(36756003)(7059030)(473944003); DIR:OUT; SFP:1101; SCL:1; SRVR:BL2PR03MB1873; H:tx30smr01.am.freescale.net; FPR:; SPF:Fail; MLV:sfv; MX:1; A:1; LANG:en; X-Microsoft-Exchange-Diagnostics: 1; BY2FFO11FD024; 1:CiNkK57YqJaL1p8wd7BjrFV5I9gbS/WPGaVm86ERoyARgA34B+8A41Lr1mpK7ODQBo0psZDribuBYeCS835Hhr83SeNbPFUa1nG3Qx6Oi7Pgs8VkCczZGCn5znSIG2KmY5EGuqNw3qE5zhawKQOXuj+Jpkab/HX1mzsgqZy/lHOplY9jGutwgbHzH9dDASunHJcJbAE4CxWjQzNtKp04akNBlsAPsavbCrTYppa0urP7jnBWX+1JSeWM4oiZzdKhfxvxQ9vOwfyYQZ7qFyvVadqsoLfOR8mHfIsAQoTMxLFpByEQTiWyngXoRmWFJbe1eTipRMV2s1OzmSUMI3nWphYdf43/P5T7p+HpIBVJuLJ6DFVHb2BWkJI3lqUjZ9MoR210+JEKTUoZiPUucO6b7m4hIWhb4o86m81zkR/IcvMqMXkpjXcV45CgecdFmz+lXgdV3VCDYgavAAYkBQkkR9KQ6/SHqx8v++BunKmcIvq62oyc+4pehF1O9zfmGc4JLxbqhPd2lVpsNOm2jI3h+PmqcLkD9ic9+5uzEuBVabCOO4BGLPXS/ASKUmFbsrE4szkt8xPggPSGUSKjckh6205SmBKU8vyGmcADc7Znm++OMOW5plV+gyuPhvD+REKmlnK6UThRgUOb2Ufpp7+Q8Vo21iXZlQvMX01PllrSfVSc8QyM1cYIxZ1xXWIxhDxA MIME-Version: 1.0 X-MS-Office365-Filtering-Correlation-Id: 3889efe6-7d9d-4db9-97df-08d38dd57169 X-Microsoft-Exchange-Diagnostics: 1; BL2PR03MB1873; 2:RC9sD57IhE/BLAtJVHIkLbbCB2s62Vb+K/Y8tsF8PwyM74P6lweNBVQa8lLzeHxt3rvKmD4lyv0dPwKwgtNccnkxMs5LHqNENzsEVbNYdy3nCiEIJlDdu7BV1tesIBV+GN7P0hKRHnCwlAqq//if+OMrZ7MRzE42NaMM/LnISivDtnzdnDLCk1Wub3AD45i0; 3:OCq8ibTxC3keISJUp7OIGzk+i756jeToM9gSM/fMxgd3ax9ZYFCY+YxQ5qK/5CRl/0BmMFnYZb4BDdr4OANa680DN+mVyhRbR2YpUM3gFw11EtyBFUiHxshhLCx93BY5aTQDGOwAdKUb99DaLPzsDOWB5Y7QQt2ZQw+eLu+eSnXdvPHSvaz74JibXOPkIrVR9smPFu93W1qASnhlMvbIZp5DJaXTqQk+hSfiroNJ95s=; 25:IXv4CDqJFe6Z4LeSMRcOC+hDxmHYoa7I4MtEX3R1hnz88coseyUS6Y++IAAooJHxcu6KEpCkiUlg7gG4/fFE6l69WJYpPvjALKi69F1drrMT3c4mtoNlQnjNfR2yI6j86xwmJUauBBDz982wr5u5/TjtATAS2Gl3RZT6+xZ0J78ySUBEEf+2nbJuvwOhhgxa+o0iXIxEtCFuF0QJTOB5XV3ZhLfad3KoCy4a7DJXeNQbtA1kzIcrB4RicXPvGpIl X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BL2PR03MB1873; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:(185117386973197); X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(601004)(2401047)(5005006)(13024025)(13018025)(13023025)(13015025)(8121501046)(13017025)(10201501046)(3002001)(6055026); SRVR:BL2PR03MB1873; BCL:0; PCL:0; RULEID:(400006); SRVR:BL2PR03MB1873; X-Microsoft-Exchange-Diagnostics: 1; BL2PR03MB1873; 4:/ilLdYJ849bjWHJXOi/t8NRc69yBrwrjnlDhPeSqUYLNH/pIkQImA7UFTkixBAu2zl6Q1+jsysH+/yRuB9W/b6ms3nsyZR2115ywNakKOMNNZU8FA41cnChzUCpf827zy3aa/kII9vObTFiCAxsEkqMx4vSp/gZyLTdTFH/WkqKingKfQ92fzbL3XOAjmPgkKcD5ILhMuSyYYHVWm/3BpYacMCYxQG7x649le2jYrWFK/EVyOKHhl2doVSDt0/xsMn0fIAOCM6hFva+wLbURdAc5kNXXD4R6h6wPCabYREyPlWgqqebUWFL2nGvFKYHHlWk11+XEcKYlvRtqs6ck6/g8/No0e4EuaVHvtmL7G7jaHsGfXAEVREwIk8ImVBzC48gm5J1cUckKRUZYSvliiI+Hs8idV7MOuc8zgNtCGN4he+NIiODZsgW2I3ojMr1nUk4m94LCCOhQBURNFBSolfu9Gr6OnUfoAFZdo3zsFwcAkU792RgKREJr2yneF1UxJPTry3SDZHoxT14Y90rxdg== X-Forefront-PRVS: 096507C068 X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; BL2PR03MB1873; 23:6rvuQ4htooqyd/yMMLp1KiPchgK6UXHexecnP+yco?= =?us-ascii?Q?S//f1DS97F5+xDiRIBmu/6BpTV9jmPhT/ZGRWCFc/W+ir/zVRemBIXr6XiVp?= =?us-ascii?Q?6BNosgOjb5U5jbupVF5WO3WqIpX6w7dKc15IlQvSE829hz1J8OobZmEbIxQG?= =?us-ascii?Q?bMNMhQC2ZLc4zto37bBHbGxLR5wr6GMaC170wU7n52ZI9y0gA+hQMOXcXd0q?= =?us-ascii?Q?/PXTJT3q852iBhGExdJ/bPDrtEU8ADKOjKz6deEqHVdDOkk2tlpmrbnbzP0z?= =?us-ascii?Q?nlwxZkhCc1mcgd6xFiERS4V3LmB6xhpzgF27WQswxeUxWLve60jA/JHVqoEE?= =?us-ascii?Q?ZEko3Ty6uCii+kbi0Gv0ndpj2wryZuIZachl9C6bw5FwAsjgJMyOUjWPiLrg?= =?us-ascii?Q?oyVGHQVmrRQ04+sykoK/qsfMXXy27qe+r5tWLP8YIjyP7QNhLbwUR7pq205k?= =?us-ascii?Q?LP18UEvQHDFpEfqmeQ1N8eHVD1WMu5+pzpCX0kMlbzBuHCkuXS3lPp/nF4FJ?= =?us-ascii?Q?dndA2qhNdVIb3cD+8+99XPggQ3Zr/gbrT3JzxPzLBPqBUk2pzdzTl5ZxbP1+?= =?us-ascii?Q?Nri+cNz5JCaNcgmIXgHKNy6pf/rCZ4YpHGv46Yu3GWTkpsx3ougMRVnty3jS?= =?us-ascii?Q?597lO4gB9HdDdQO+weQ8BAAL4qJpE7y4aTjK3Oogu/yhA5cPsy1532pzT0i9?= =?us-ascii?Q?kYsb0yRKja2dxGSe9mki3m1va8mBfV5cFkv2kL9fpdkdf87U7S3ErJhc8adP?= =?us-ascii?Q?xIKMolPey5nHv4WlXvYFMcgsMJ6LbM5jYHLt1Brlpg1s5Q6tBOqovpuAWZFt?= =?us-ascii?Q?CgvydsQobKDBCKbNv5r3RHCv46qr1y7FD6JOEcelipYSqwvYu7Opuz3Whr5E?= =?us-ascii?Q?jQfF1jR77LQQ/dr9xAgznCJsAq0PqSEAsphxGgn4ZrGyE99K+tDCz2YLulAo?= =?us-ascii?Q?fNz11uBzw1Mk33jdT6P3/9oIqo/p/GZ2v2Zx0PD+SC+hEU49ti9c+Pl/pU9F?= =?us-ascii?Q?dYvkB+ici95Nh2OIu90UP0AFWC6IWAFAD/agOCMrIR4fIpJzRqPLpRQA3CcZ?= =?us-ascii?Q?Rlh+bTrGW9sH5UjXNEixOK34jKrRzE+tNCR2klHQ/Qjo26F0XNcxlYrRAnAE?= =?us-ascii?Q?04sWiZFu20=3D?= X-Microsoft-Exchange-Diagnostics: 1; BL2PR03MB1873; 5:BUaHafj6r6axkpwcwh6ur77uA2KH4cbuTcAJ0oX8+3/nAr91FgdPiI4gKOMioXASRezKQMGPP8tw1cjyY2uuIFbCU9m5W/hFEpFMzeYjmEXVU+p2BchuZ5NVhB+pgWcWLvR6ah29zVWXzVksMUsFzdK6r+DV0geumLbe3X1wRtg=; 24:nwb8aRIksXdt1GyY/lzFjMgFnPzxPCT5a7W1i7AaTdJMoCA8MlDjn3aKvwzuoVk2mSwo+SFXVVFgH1SK3iLvMsCTVXz9ee5BfnOB328ZDGU= SpamDiagnosticOutput: 1:23 SpamDiagnosticMetadata: NSPM X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jun 2016 06:40:25.7639 (UTC) X-MS-Exchange-CrossTenant-Id: 5afe0b00-7697-4969-b663-5eab37d5f47e X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e; Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL2PR03MB1873 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Add tdm clock configuration in both qe clock system and ucc fast controller. Signed-off-by: Zhao Qiang --- Changes for v2: - break codes getting clock_bits and source to smaller functions. - add __iomem to qe_mux_reg - add bits operation functions for qe and use it - retrun -EINVAL when clock_bits is invalid Changes for v3: - adjust some incorrect indentations drivers/soc/fsl/qe/ucc.c | 450 ++++++++++++++++++++++++++++++++++++++++++ drivers/soc/fsl/qe/ucc_fast.c | 36 ++++ include/soc/fsl/qe/qe.h | 16 ++ include/soc/fsl/qe/ucc.h | 4 + include/soc/fsl/qe/ucc_fast.h | 1 + 5 files changed, 507 insertions(+) diff --git a/drivers/soc/fsl/qe/ucc.c b/drivers/soc/fsl/qe/ucc.c index b59d335..c646d87 100644 --- a/drivers/soc/fsl/qe/ucc.c +++ b/drivers/soc/fsl/qe/ucc.c @@ -25,6 +25,12 @@ #include #include +#define UCC_TDM_NUM 8 +#define RX_SYNC_SHIFT_BASE 30 +#define TX_SYNC_SHIFT_BASE 14 +#define RX_CLK_SHIFT_BASE 28 +#define TX_CLK_SHIFT_BASE 12 + int ucc_set_qe_mux_mii_mng(unsigned int ucc_num) { unsigned long flags; @@ -210,3 +216,447 @@ int ucc_set_qe_mux_rxtx(unsigned int ucc_num, enum qe_clock clock, return 0; } + +static int ucc_get_tdm_common_clk(u32 tdm_num, enum qe_clock clock) +{ + int clock_bits = -EINVAL; + + /* + * for TDM[0, 1, 2, 3], TX and RX use common + * clock source BRG3,4 and CLK1,2 + * for TDM[4, 5, 6, 7], TX and RX use common + * clock source BRG12,13 and CLK23,24 + */ + switch (tdm_num) { + case 0: + case 1: + case 2: + case 3: + switch (clock) { + case QE_BRG3: + clock_bits = 1; + break; + case QE_BRG4: + clock_bits = 2; + break; + case QE_CLK1: + clock_bits = 4; + break; + case QE_CLK2: + clock_bits = 5; + break; + default: + break; + } + break; + case 4: + case 5: + case 6: + case 7: + switch (clock) { + case QE_BRG12: + clock_bits = 1; + break; + case QE_BRG13: + clock_bits = 2; + break; + case QE_CLK23: + clock_bits = 4; + break; + case QE_CLK24: + clock_bits = 5; + break; + default: + break; + } + break; + default: + break; + } + + return clock_bits; +} + +static int ucc_get_tdm_rx_clk(u32 tdm_num, enum qe_clock clock) +{ + int clock_bits = -EINVAL; + + switch (tdm_num) { + case 0: + switch (clock) { + case QE_CLK3: + clock_bits = 6; + break; + case QE_CLK8: + clock_bits = 7; + break; + default: + break; + } + break; + case 1: + switch (clock) { + case QE_CLK5: + clock_bits = 6; + break; + case QE_CLK10: + clock_bits = 7; + break; + default: + break; + } + break; + case 2: + switch (clock) { + case QE_CLK7: + clock_bits = 6; + break; + case QE_CLK12: + clock_bits = 7; + break; + default: + break; + } + break; + case 3: + switch (clock) { + case QE_CLK9: + clock_bits = 6; + break; + case QE_CLK14: + clock_bits = 7; + break; + default: + break; + } + break; + case 4: + switch (clock) { + case QE_CLK11: + clock_bits = 6; + break; + case QE_CLK16: + clock_bits = 7; + break; + default: + break; + } + break; + case 5: + switch (clock) { + case QE_CLK13: + clock_bits = 6; + break; + case QE_CLK18: + clock_bits = 7; + break; + default: + break; + } + break; + case 6: + switch (clock) { + case QE_CLK15: + clock_bits = 6; + break; + case QE_CLK20: + clock_bits = 7; + break; + default: + break; + } + break; + case 7: + switch (clock) { + case QE_CLK17: + clock_bits = 6; + break; + case QE_CLK22: + clock_bits = 7; + break; + default: + break; + } + break; + } + + return clock_bits; +} + +static int ucc_get_tdm_tx_clk(u32 tdm_num, enum qe_clock clock) +{ + int clock_bits = -EINVAL; + + switch (tdm_num) { + case 0: + switch (clock) { + case QE_CLK4: + clock_bits = 6; + break; + case QE_CLK9: + clock_bits = 7; + break; + default: + break; + } + break; + case 1: + switch (clock) { + case QE_CLK6: + clock_bits = 6; + break; + case QE_CLK11: + clock_bits = 7; + break; + default: + break; + } + break; + case 2: + switch (clock) { + case QE_CLK8: + clock_bits = 6; + break; + case QE_CLK13: + clock_bits = 7; + break; + default: + break; + } + break; + case 3: + switch (clock) { + case QE_CLK10: + clock_bits = 6; + break; + case QE_CLK15: + clock_bits = 7; + break; + default: + break; + } + break; + case 4: + switch (clock) { + case QE_CLK12: + clock_bits = 6; + break; + case QE_CLK17: + clock_bits = 7; + break; + default: + break; + } + break; + case 5: + switch (clock) { + case QE_CLK14: + clock_bits = 6; + break; + case QE_CLK19: + clock_bits = 7; + break; + default: + break; + } + break; + case 6: + switch (clock) { + case QE_CLK16: + clock_bits = 6; + break; + case QE_CLK21: + clock_bits = 7; + break; + default: + break; + } + break; + case 7: + switch (clock) { + case QE_CLK18: + clock_bits = 6; + break; + case QE_CLK3: + clock_bits = 7; + break; + default: + break; + } + break; + } + + return clock_bits; +} + +/* tdm_num: TDM A-H port num is 0-7 */ +static int ucc_get_tdm_rxtx_clk(enum comm_dir mode, u32 tdm_num, + enum qe_clock clock) +{ + int clock_bits; + + clock_bits = ucc_get_tdm_common_clk(tdm_num, clock); + if (clock_bits > 0) + return clock_bits; + if (mode == COMM_DIR_RX) + clock_bits = ucc_get_tdm_rx_clk(tdm_num, clock); + if (mode == COMM_DIR_TX) + clock_bits = ucc_get_tdm_tx_clk(tdm_num, clock); + return clock_bits; +} + +static u32 ucc_get_tdm_clk_shift(enum comm_dir mode, u32 tdm_num) +{ + u32 shift; + + shift = (mode == COMM_DIR_RX) ? RX_CLK_SHIFT_BASE : TX_CLK_SHIFT_BASE; + if (tdm_num < 4) + shift -= tdm_num * 4; + else + shift -= (tdm_num - 4) * 4; + + return shift; +} + +int ucc_set_tdm_rxtx_clk(u32 tdm_num, enum qe_clock clock, + enum comm_dir mode) +{ + int clock_bits; + u32 shift; + struct qe_mux __iomem *qe_mux_reg; + __be32 __iomem *cmxs1cr; + + qe_mux_reg = &qe_immr->qmx; + + if (tdm_num > 7 || tdm_num < 0) + return -EINVAL; + + /* The communications direction must be RX or TX */ + if (mode != COMM_DIR_RX && mode != COMM_DIR_TX) + return -EINVAL; + + clock_bits = ucc_get_tdm_rxtx_clk(mode, tdm_num, clock); + if (clock_bits < 0) + return -EINVAL; + + shift = ucc_get_tdm_clk_shift(mode, tdm_num); + + cmxs1cr = (tdm_num < 4) ? &qe_mux_reg->cmxsi1cr_l : + &qe_mux_reg->cmxsi1cr_h; + + qe_clrsetbits32(cmxs1cr, QE_CMXUCR_TX_CLK_SRC_MASK << shift, + clock_bits << shift); + + return 0; +} + +static int ucc_get_tdm_sync_source(u32 tdm_num, enum qe_clock clock, + enum comm_dir mode) +{ + int source = -EINVAL; + + if (mode == COMM_DIR_RX && clock == QE_RSYNC_PIN) { + source = 0; + return source; + } + if (mode == COMM_DIR_TX && clock == QE_TSYNC_PIN) { + source = 0; + return source; + } + + switch (tdm_num) { + case 0: + case 1: + switch (clock) { + case QE_BRG9: + source = 1; + break; + case QE_BRG10: + source = 2; + break; + default: + break; + } + break; + case 2: + case 3: + switch (clock) { + case QE_BRG9: + source = 1; + break; + case QE_BRG11: + source = 2; + break; + default: + break; + } + break; + case 4: + case 5: + switch (clock) { + case QE_BRG13: + source = 1; + break; + case QE_BRG14: + source = 2; + break; + default: + break; + } + break; + case 6: + case 7: + switch (clock) { + case QE_BRG13: + source = 1; + break; + case QE_BRG15: + source = 2; + break; + default: + break; + } + break; + } + + return source; +} + +static u32 ucc_get_tdm_sync_shift(enum comm_dir mode, u32 tdm_num) +{ + u32 shift; + + shift = (mode == COMM_DIR_RX) ? RX_SYNC_SHIFT_BASE : RX_SYNC_SHIFT_BASE; + shift -= tdm_num * 2; + + return shift; +} + +int ucc_set_tdm_rxtx_sync(u32 tdm_num, enum qe_clock clock, + enum comm_dir mode) +{ + int source; + u32 shift; + struct qe_mux *qe_mux_reg; + + qe_mux_reg = &qe_immr->qmx; + + if (tdm_num >= UCC_TDM_NUM) + return -EINVAL; + + /* The communications direction must be RX or TX */ + if (mode != COMM_DIR_RX && mode != COMM_DIR_TX) + return -EINVAL; + + source = ucc_get_tdm_sync_source(tdm_num, clock, mode); + if (source < 0) + return -EINVAL; + + shift = ucc_get_tdm_sync_shift(mode, tdm_num); + + qe_clrsetbits32(&qe_mux_reg->cmxsi1syr, + QE_CMXUCR_TX_CLK_SRC_MASK << shift, + source << shift); + + return 0; +} diff --git a/drivers/soc/fsl/qe/ucc_fast.c b/drivers/soc/fsl/qe/ucc_fast.c index a768931..83d8d16 100644 --- a/drivers/soc/fsl/qe/ucc_fast.c +++ b/drivers/soc/fsl/qe/ucc_fast.c @@ -327,6 +327,42 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc ucc_fast_free(uccf); return -EINVAL; } + } else { + /* tdm Rx clock routing */ + if ((uf_info->rx_clock != QE_CLK_NONE) && + ucc_set_tdm_rxtx_clk(uf_info->tdm_num, uf_info->rx_clock, + COMM_DIR_RX)) { + pr_err("%s: illegal value for RX clock", __func__); + ucc_fast_free(uccf); + return -EINVAL; + } + + /* tdm Tx clock routing */ + if ((uf_info->tx_clock != QE_CLK_NONE) && + ucc_set_tdm_rxtx_clk(uf_info->tdm_num, uf_info->tx_clock, + COMM_DIR_TX)) { + pr_err("%s: illegal value for TX clock", __func__); + ucc_fast_free(uccf); + return -EINVAL; + } + + /* tdm Rx sync clock routing */ + if ((uf_info->rx_sync != QE_CLK_NONE) && + ucc_set_tdm_rxtx_sync(uf_info->tdm_num, uf_info->rx_sync, + COMM_DIR_RX)) { + pr_err("%s: illegal value for RX clock", __func__); + ucc_fast_free(uccf); + return -EINVAL; + } + + /* tdm Tx sync clock routing */ + if ((uf_info->tx_sync != QE_CLK_NONE) && + ucc_set_tdm_rxtx_sync(uf_info->tdm_num, uf_info->tx_sync, + COMM_DIR_TX)) { + pr_err("%s: illegal value for TX clock", __func__); + ucc_fast_free(uccf); + return -EINVAL; + } } /* Set interrupt mask register at UCC level. */ diff --git a/include/soc/fsl/qe/qe.h b/include/soc/fsl/qe/qe.h index f918745..c3b1dc8 100644 --- a/include/soc/fsl/qe/qe.h +++ b/include/soc/fsl/qe/qe.h @@ -244,6 +244,22 @@ static inline int qe_alive_during_sleep(void) #define qe_muram_addr cpm_muram_addr #define qe_muram_offset cpm_muram_offset +#define qe_setbits32(_addr, _v) iowrite32be(ioread32be(_addr) | (_v), (_addr)) +#define qe_clrbits32(_addr, _v) iowrite32be(ioread32be(_addr) & ~(_v), (_addr)) + +#define qe_setbits16(_addr, _v) iowrite16be(ioread16be(_addr) | (_v), (_addr)) +#define qe_clrbits16(_addr, _v) iowrite16be(ioread16be(_addr) & ~(_v), (_addr)) + +#define qe_setbits8(_addr, _v) iowrite8(ioread8(_addr) | (_v), (_addr)) +#define qe_clrbits8(_addr, _v) iowrite8(ioread8(_addr) & ~(_v), (_addr)) + +#define qe_clrsetbits32(addr, clear, set) \ + iowrite32be((ioread32be(addr) & ~(clear)) | (set), (addr)) +#define qe_clrsetbits16(addr, clear, set) \ + iowrite16be((ioread16be(addr) & ~(clear)) | (set), (addr)) +#define qe_clrsetbits8(addr, clear, set) \ + iowrite8((ioread8(addr) & ~(clear)) | (set), (addr)) + /* Structure that defines QE firmware binary files. * * See Documentation/powerpc/qe_firmware.txt for a description of these diff --git a/include/soc/fsl/qe/ucc.h b/include/soc/fsl/qe/ucc.h index 894f14c..6bbbb59 100644 --- a/include/soc/fsl/qe/ucc.h +++ b/include/soc/fsl/qe/ucc.h @@ -41,6 +41,10 @@ int ucc_set_qe_mux_mii_mng(unsigned int ucc_num); int ucc_set_qe_mux_rxtx(unsigned int ucc_num, enum qe_clock clock, enum comm_dir mode); +int ucc_set_tdm_rxtx_clk(unsigned int tdm_num, enum qe_clock clock, + enum comm_dir mode); +int ucc_set_tdm_rxtx_sync(unsigned int tdm_num, enum qe_clock clock, + enum comm_dir mode); int ucc_mux_set_grant_tsa_bkpt(unsigned int ucc_num, int set, u32 mask); diff --git a/include/soc/fsl/qe/ucc_fast.h b/include/soc/fsl/qe/ucc_fast.h index 31548b7..b2633b7 100644 --- a/include/soc/fsl/qe/ucc_fast.h +++ b/include/soc/fsl/qe/ucc_fast.h @@ -118,6 +118,7 @@ enum ucc_fast_transparent_tcrc { /* Fast UCC initialization structure */ struct ucc_fast_info { int ucc_num; + int tdm_num; enum qe_clock rx_clock; enum qe_clock tx_clock; enum qe_clock rx_sync;