From patchwork Thu Apr 28 07:01:42 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yisen.Zhuang(Zhuangyuzeng)" X-Patchwork-Id: 616013 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3qwS9T0LD7z9t5s for ; Thu, 28 Apr 2016 16:49:17 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752324AbcD1GtP (ORCPT ); Thu, 28 Apr 2016 02:49:15 -0400 Received: from szxga03-in.huawei.com ([119.145.14.66]:27401 "EHLO szxga03-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751122AbcD1GtO (ORCPT ); Thu, 28 Apr 2016 02:49:14 -0400 Received: from 172.24.1.36 (EHLO SZXEML423-HUB.china.huawei.com) ([172.24.1.36]) by szxrg03-dlp.huawei.com (MOS 4.4.3-GA FastPath queued) with ESMTP id CAV17856; Thu, 28 Apr 2016 14:43:21 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by SZXEML423-HUB.china.huawei.com (10.82.67.154) with Microsoft SMTP Server id 14.3.235.1; Thu, 28 Apr 2016 14:43:10 +0800 From: Yisen Zhuang To: , , CC: , , , , , , , , , , , , , , , Subject: [PATCH net-next 10/10] net: hns: add attribute port-mode-offset for dsaf port node Date: Thu, 28 Apr 2016 15:01:42 +0800 Message-ID: <1461826902-51368-11-git-send-email-Yisen.Zhuang@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1461826902-51368-1-git-send-email-Yisen.Zhuang@huawei.com> References: <1461826902-51368-1-git-send-email-Yisen.Zhuang@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090202.5721B10A.0005, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-05-26 15:14:31, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 8ad0b24b48dcf68e4c61f0d4ce221d2c Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Port mode offset for each dsaf port is different. The current code is not so readability. This patch adds configuration named port-mode-offset to make the code simple and more readability. If port-mode-offset isn't exists, default value 0 will be used. Signed-off-by: Daode Huang Signed-off-by: Yisen Zhuang --- .../devicetree/bindings/net/hisilicon-hns-dsaf.txt | 2 + drivers/net/ethernet/hisilicon/hns/hns_dsaf_mac.c | 10 +++++ drivers/net/ethernet/hisilicon/hns/hns_dsaf_mac.h | 1 + drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c | 44 ++++++++++------------ 4 files changed, 32 insertions(+), 25 deletions(-) diff --git a/Documentation/devicetree/bindings/net/hisilicon-hns-dsaf.txt b/Documentation/devicetree/bindings/net/hisilicon-hns-dsaf.txt index 72efe71..31d9d19 100644 --- a/Documentation/devicetree/bindings/net/hisilicon-hns-dsaf.txt +++ b/Documentation/devicetree/bindings/net/hisilicon-hns-dsaf.txt @@ -45,6 +45,8 @@ Required properties: cpld-syscon. - port-rst-offset: is offset of reset field for each port in dsaf. Its value depends on the hardware user manual. +- port-mode-offset: is offset of port mode field for each port in dsaf. Its + value depends on the hardware user manual. [1] Documentation/devicetree/bindings/net/phy.txt diff --git a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_mac.c b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_mac.c index 190477e..d825277 100644 --- a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_mac.c +++ b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_mac.c @@ -665,6 +665,7 @@ static int hns_mac_get_info(struct hns_mac_cb *mac_cb) mac_cb->max_frm = MAC_DEFAULT_MTU; mac_cb->tx_pause_frm_time = MAC_DEFAULT_PAUSE_TIME; mac_cb->port_rst_off = mac_cb->mac_id; + mac_cb->port_mode_off = 0; /* if the dsaf node doesn't contain a port subnode, * parse the old dts to get phy-handle from dsaf node @@ -704,6 +705,15 @@ static int hns_mac_get_info(struct hns_mac_cb *mac_cb) mac_cb->mac_id); } + ret = fwnode_property_read_u32(mac_cb->fw_port, + "port-mode-offset", + &mac_cb->port_mode_off); + if (ret) { + dev_dbg(mac_cb->dev, + "mac%d port-mode-offset not found, use default value.\n", + mac_cb->mac_id); + } + syscon = syscon_node_to_regmap( of_parse_phandle(to_of_node(mac_cb->fw_port), "cpld-syscon", 0)); diff --git a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_mac.h b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_mac.h index 7be7104..97ce9a7 100644 --- a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_mac.h +++ b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_mac.h @@ -319,6 +319,7 @@ struct hns_mac_cb { struct regmap *cpld_ctrl; u32 cpld_ctrl_reg; u32 port_rst_off; + u32 port_mode_off; struct mac_entry_idx addr_entry_idx[DSAF_MAX_VM_NUM]; u8 sfp_prsnt; u8 cpld_led_value; diff --git a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c index fc3056e..eecdb14 100644 --- a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c +++ b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c @@ -265,37 +265,31 @@ phy_interface_t hns_mac_get_phy_if(struct hns_mac_cb *mac_cb) { u32 mode; u32 reg; - u32 shift; - u32 phy_offset; bool is_ver1 = AE_IS_VER1(mac_cb->dsaf_dev->dsaf_ver); int mac_id = mac_cb->mac_id; - phy_interface_t phy_if = PHY_INTERFACE_MODE_NA; + phy_interface_t phy_if; - if (is_ver1 && HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev)) { - phy_if = PHY_INTERFACE_MODE_SGMII; - } else if (mac_id >= 0 && mac_id <= 3 && - !HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev)) { - reg = is_ver1 ? HNS_MAC_HILINK4_REG : HNS_MAC_HILINK4V2_REG; - mode = dsaf_read_sub(mac_cb->dsaf_dev, reg); - /* mac_id 0, 1, 2, 3 ---> hilink4 lane 0, 1, 2, 3 */ - shift = is_ver1 ? 0 : mac_id; - if (dsaf_get_bit(mode, shift)) - phy_if = PHY_INTERFACE_MODE_XGMII; + if (is_ver1) { + if (HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev)) + return PHY_INTERFACE_MODE_SGMII; + + if (mac_id >= 0 && mac_id <= 3) + reg = HNS_MAC_HILINK4_REG; else - phy_if = PHY_INTERFACE_MODE_SGMII; - } else { - reg = is_ver1 ? HNS_MAC_HILINK3_REG : HNS_MAC_HILINK3V2_REG; - mode = dsaf_read_sub(mac_cb->dsaf_dev, reg); - /* mac_id 4, 5,---> hilink3 lane 2, 3 - * debug port 0(6), 1(7) ---> hilink3 lane 0, 1 - */ - phy_offset = mac_cb->dsaf_dev->reset_offset - 1; - shift = is_ver1 ? 0 : mac_id >= 4 ? mac_id - 2 : phy_offset; - if (dsaf_get_bit(mode, shift)) - phy_if = PHY_INTERFACE_MODE_XGMII; + reg = HNS_MAC_HILINK3_REG; + } else{ + if (!HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev) && mac_id <= 3) + reg = HNS_MAC_HILINK4V2_REG; else - phy_if = PHY_INTERFACE_MODE_SGMII; + reg = HNS_MAC_HILINK3V2_REG; } + + mode = dsaf_read_sub(mac_cb->dsaf_dev, reg); + if (dsaf_get_bit(mode, mac_cb->port_mode_off)) + phy_if = PHY_INTERFACE_MODE_XGMII; + else + phy_if = PHY_INTERFACE_MODE_SGMII; + return phy_if; }