| Message ID | 1457080877-13456-3-git-send-email-xavier.huwei@huawei.com |
|---|---|
| State | Changes Requested, archived |
| Delegated to: | David Miller |
| Headers | show |
Hello. On 3/4/2016 11:41 AM, Wei Hu(Xavier) wrote: > This submit add binding file and dts file. > > Signed-off-by: Wei Hu(Xavier) <xavier.huwei@huawei.com> > Signed-off-by: oulijun <oulijun@huawei.com> > --- > .../bindings/infiniband/hisilicon-hns-roce.txt | 68 ++++++++++++++++++++++ > 1 file changed, 68 insertions(+) > create mode 100644 Documentation/devicetree/bindings/infiniband/hisilicon-hns-roce.txt > > diff --git a/Documentation/devicetree/bindings/infiniband/hisilicon-hns-roce.txt b/Documentation/devicetree/bindings/infiniband/hisilicon-hns-roce.txt > new file mode 100644 > index 0000000..8004641 > --- /dev/null > +++ b/Documentation/devicetree/bindings/infiniband/hisilicon-hns-roce.txt > @@ -0,0 +1,68 @@ > +HiSilicon RoCE DT description > + > +HiSilicon RoCE engine is a part of network subsystem. > +It works depending on other part of network wubsytem, such as, gmac and > +dsa fabric. > + > +Additional properties are described here: > + > +Required properties: > +- compatible: Should contain "hisilicon,hns-roce-v1". > +- reg: Physical base address of the roce driver and > +length of memory mapped region. > +- eth-handle: phandle, specifies a reference to a node > +representing a ethernet device. > +- dsaf-handle: phandle, specifies a reference to a node > +representing a dsaf device. > +- #address-cells: must be 2 > +- #size-cells: must be 2 > +Optional properties: > +- dma-coherent: Present if DMA operations are coherent. > +- interrupt-parent: the interrupt parent of this device. > +- interrupts: should contain 32 completion event irq,1 async event irq > +and 1 event overflow irq. The "interrupt-names" prop is very desirable for so many interrupts. > +Example: > + rocee@0xc4000000 { The node names should be generic and "0x" should be omitted, i.e. "infiniband@c4000000". MBR, Sergei
Hi Sergei Shtylyov, thanks for reviewing I have modified the binding referred to your advice and the bindings of other module. I will send a new patch in future. Thanks Lijun Ou On 2016/3/4 21:51, Sergei Shtylyov wrote: > Hello. > > On 3/4/2016 11:41 AM, Wei Hu(Xavier) wrote: > >> This submit add binding file and dts file. >> >> Signed-off-by: Wei Hu(Xavier) <xavier.huwei@huawei.com> >> Signed-off-by: oulijun <oulijun@huawei.com> >> --- >> .../bindings/infiniband/hisilicon-hns-roce.txt | 68 ++++++++++++++++++++++ >> 1 file changed, 68 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/infiniband/hisilicon-hns-roce.txt >> >> diff --git a/Documentation/devicetree/bindings/infiniband/hisilicon-hns-roce.txt b/Documentation/devicetree/bindings/infiniband/hisilicon-hns-roce.txt >> new file mode 100644 >> index 0000000..8004641 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/infiniband/hisilicon-hns-roce.txt >> @@ -0,0 +1,68 @@ >> +HiSilicon RoCE DT description >> + >> +HiSilicon RoCE engine is a part of network subsystem. >> +It works depending on other part of network wubsytem, such as, gmac and >> +dsa fabric. >> + >> +Additional properties are described here: >> + >> +Required properties: >> +- compatible: Should contain "hisilicon,hns-roce-v1". >> +- reg: Physical base address of the roce driver and >> +length of memory mapped region. >> +- eth-handle: phandle, specifies a reference to a node >> +representing a ethernet device. >> +- dsaf-handle: phandle, specifies a reference to a node >> +representing a dsaf device. >> +- #address-cells: must be 2 >> +- #size-cells: must be 2 >> +Optional properties: >> +- dma-coherent: Present if DMA operations are coherent. >> +- interrupt-parent: the interrupt parent of this device. >> +- interrupts: should contain 32 completion event irq,1 async event irq >> +and 1 event overflow irq. > > The "interrupt-names" prop is very desirable for so many interrupts. > >> +Example: >> + rocee@0xc4000000 { > > The node names should be generic and "0x" should be omitted, i.e. "infiniband@c4000000". > > MBR, Sergei > > > . >
diff --git a/Documentation/devicetree/bindings/infiniband/hisilicon-hns-roce.txt b/Documentation/devicetree/bindings/infiniband/hisilicon-hns-roce.txt new file mode 100644 index 0000000..8004641 --- /dev/null +++ b/Documentation/devicetree/bindings/infiniband/hisilicon-hns-roce.txt @@ -0,0 +1,68 @@ +HiSilicon RoCE DT description + +HiSilicon RoCE engine is a part of network subsystem. +It works depending on other part of network wubsytem, such as, gmac and +dsa fabric. + +Additional properties are described here: + +Required properties: +- compatible: Should contain "hisilicon,hns-roce-v1". +- reg: Physical base address of the roce driver and +length of memory mapped region. +- eth-handle: phandle, specifies a reference to a node +representing a ethernet device. +- dsaf-handle: phandle, specifies a reference to a node +representing a dsaf device. +- #address-cells: must be 2 +- #size-cells: must be 2 +Optional properties: +- dma-coherent: Present if DMA operations are coherent. +- interrupt-parent: the interrupt parent of this device. +- interrupts: should contain 32 completion event irq,1 async event irq +and 1 event overflow irq. +Example: + rocee@0xc4000000 { + compatible = "hisilicon,hns-roce-v1"; + reg = <0x0 0xc4000000 0x0 0x100000>; + dma-coherent; + eth-handle = <ð2 ð3 ð4 ð5 ð6 ð7>; + dsaf-handle = <&soc0_dsa>; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mbigen_dsa>; + interrupts = <722 1>, + <723 1>, + <724 1>, + <725 1>, + <726 1>, + <727 1>, + <728 1>, + <729 1>, + <730 1>, + <731 1>, + <732 1>, + <733 1>, + <734 1>, + <735 1>, + <736 1>, + <737 1>, + <738 1>, + <739 1>, + <740 1>, + <741 1>, + <742 1>, + <743 1>, + <744 1>, + <745 1>, + <746 1>, + <747 1>, + <748 1>, + <749 1>, + <750 1>, + <751 1>, + <752 1>, + <753 1>, + <785 1>, + <754 4>; + };